Pre-bond TSV Testing via Ring Oscillator Frequency Shifts
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Solution Overview
Problem
The semiconductor industry faces challenges in pre-bond testing of 3D ICs due to defects like voids and pinholes in through-silicon vias (TSVs), which are difficult to access and probe, leading to low yields and potential short circuits.
Innovation Solution
A non-invasive pre-bond testing method using ring oscillators configured from I/O segments on a chip, detecting resistive open and leakage faults by analyzing variations in the oscillating output signal, without the need for external probing equipment, utilizing standard cells and multiple supply voltage levels for increased sensitivity and robustness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Difficulty of detecting and measuring
If mechanical probing is used to access TSVs after wafer thinning, then TSV testing becomes possible, but equipment requirements become extremely strict and complex
Solution Approach 1:
The patent replaces mechanical probing with an electrical measurement approach. Ring oscillators are configured to measure electrical characteristics (frequency, period) of TSV paths, eliminating the need for mechanical probe contacts. This substitution transforms the testing method from mechanical to electrical domain, resolving the contradiction between enabling TSV testing and avoiding complex equipment requirements.
Solution Approach 2:
The patent introduces ring oscillators as an intermediary measurement system. Instead of directly probing TSVs with external equipment, the ring oscillators serve as mediators that convert TSV electrical characteristics into measurable oscillation signals. This intermediary approach enables indirect measurement, avoiding the need for direct mechanical probe-TSV contact and its associated equipment complexity.
2Productivity
If pre-bond testing is performed to increase KGD probability, then product yield improves, but test access becomes more difficult due to buried TSVs
Solution Approach 1:
The patent performs ring oscillator configuration and testing before the bonding process (pre-bond). This preliminary action allows defects to be identified early when TSVs are still accessible through electrical measurement, enabling sorting of good dies before bonding. The timing is critical: testing occurs before bonding but after wafer thinning, when TSVs can be electrically accessed via the front-side logic connections.
Solution Approach 2:
The patent segments the testing process into separate phases: pre-bond testing using ring oscillators, followed by bonding, and then final testing. This segmentation allows targeted testing of TSV-related defects before bonding, while other testing can be performed after bonding. The segmentation enables yield improvement by removing defective dies early in the process.
3Measurement precision
If multiple voltage levels are used for testing, then detection sensitivity and robustness increase, but testing complexity and time increase
Solution Approach 1:
The patent employs periodic voltage switching during ring oscillator operation. The test sequence alternates between different voltage levels in a periodic manner, allowing the system to capture electrical characteristics at multiple voltage points without requiring simultaneous multi-voltage application. This periodic approach enables enhanced detection sensitivity through voltage-dependent characteristic analysis while managing testing time through efficient sequential measurement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method allows for effective detection of TSV defects without invasive probing, reducing testing costs and design overhead, and improving product yield by identifying faults before bonding, thus enhancing the reliability of 3D ICs.
Implementation Method 1
detecting resistive open faults and leakage faults in TSVs from characteristics of the oscillating output signal
Implementation Method 2
The TSV acts as a shunt-connected capacitor—when defect free—and includes a load resistance when the TSV contains a defect
Data Source
AI summary
A design for test (DfT) architecture is provided that enables pre-bond parametric testing of through-silicon vias (TSVs). A grouping of N number of input/output (I/O) segments are configured to receive a test signal in a feedback loop, where each I/O segment includes one or more buffers (or inverters) and a TSV connected at one end to the one or more buffers. The TSV acts as a shunt-connected capacitor—when defect free—and includes a load resistance when the TSV contains a defect. Each I/O segment can also include one or two multiplexers to control whether the I/O segment receives a test or functional signal and, optionally, whether the I/O segment is bypassed or included in the ring oscillator. The varying loads caused by the defects cause variations in the delay across the buffers (or inverters) of an I/O segment that can be detected in the output signal.