Simultaneous TSV and Routing Layer Deposition in Semiconductor Substrates
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Solution Overview
Problem
Conventional processes for forming through silicon vias (TSVs) in semiconductor substrates are inefficient, requiring multiple processing stages and resulting in excess conductive material waste, as well as potential polishing defects due to non-uniform pressure distribution during surface preparation.
Innovation Solution
Simultaneously forming conductive material portions for both through vias and routing traces without intervening stages, using techniques like pulsed chemical vapor deposition, and reducing processing steps to enhance homogeneity and reliability, while eliminating excess material and associated waste.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If blanket plating is used to form TSVs, then the number of processing steps is reduced, but a large amount of excess conductive material is created on the substrate surface
Solution Approach 1:
The patent combines the TSV formation and routing trace formation into a single simultaneous plating operation. By merging these two separate processes into one, the invention eliminates the need for multiple processing steps while precisely controlling conductive material deposition only where needed (in via holes and trace patterns), thereby avoiding excess material waste.
Solution Approach 2:
The invention creates a multi-functional plating process that simultaneously performs multiple tasks: forming TSVs, creating routing traces, and defining precise conductive patterns all in one operation. This universal approach replaces sequential specialized processes, improving productivity while eliminating material waste through precise control.
2Loss of substance
If pattern plating with resist mask is used to form TSVs, then conductive material waste is reduced, but additional processing stages are required
Solution Approach 1:
The patent merges TSV formation and routing trace formation into a single simultaneous plating operation, eliminating the need for separate resist masking, patterning, and multiple plating steps. This consolidation reduces device complexity while maintaining precise control over conductive material placement.
Solution Approach 2:
The invention uses preliminary patterning of the resist layer to define both via hole locations and routing trace patterns before the single plating operation. This preliminary action enables the subsequent unified plating process to deposit conductive material precisely where needed without requiring additional processing stages.
3Reliability
If conventional TSV processes are used, then manufacturing experience is available, but polishing defects occur due to non-uniform pressure distribution
Solution Approach 1:
By combining TSV and routing trace formation into a single process, the invention creates a larger, more continuous conductive surface area on the substrate. This merged structure distributes polishing pressure more uniformly across the surface, preventing the non-uniform pressure distribution that causes polishing defects in conventional separate-process approaches.
Solution Approach 2:
The invention creates a more homogeneous conductive material distribution across the substrate surface by simultaneously forming TSVs and routing traces. This homogeneous structure ensures uniform pressure distribution during subsequent polishing operations, eliminating the pressure concentration points that cause defects in conventional processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing costs, enhances the reliability of semiconductor dies by eliminating intermediate processing stages, and minimizes polishing defects by ensuring uniform pressure distribution across a larger conductive surface area.
Implementation Method 1
pulsed chemical vapor deposition
Data Source
Figure 1A
Figure 1B
Figure 1C
AI summary
Through vias and conductive routing layers in semiconductor substrates and associated methods of manufacturing are disclosed herein. In one embodiment, a method for processing a semiconductor substrate includes forming an aperture in a semiconductor substrate and through a dielectric on the semiconductor substrate. The aperture has a first end open at the dielectric and a second end opposite the first end. The method can also include forming a plurality of depressions in the dielectric, and simultaneously depositing a conductive material into the aperture and at least some of the depressions.