Through-Silicon Via Formation Using Sacrificial Dielectric Stacking
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Solution Overview
Problem
Current methods for forming through-silicon vias (TSVs) in semiconductor fabrication are inefficient and require complex processes, including the use of hard masks and can result in copper residue on the wafer surface, limiting the ability to achieve higher circuit density in three-dimensional integrated circuits.
Innovation Solution
A method involving the formation of dielectric layers with sacrificial stacking structures, followed by etching to create recesses in the semiconductor substrate, which are then filled with conductive material to form TSVs, allowing for efficient electrical connections between stacked dice without the need for a large carrier substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional TSV formation methods using hard masks and etching are employed, then through-silicon vias can be formed to enable 3D IC connections, but copper residue remains on the wafer surface and the process complexity increases
Solution Approach 1:
A sacrificial stacking structure (intermediary material) is introduced as a mediator during the TSV formation process. This sacrificial material is deposited conformally and then selectively removed through recesses, serving as a temporary intermediary that enables precise copper deposition without leaving residue on the wafer surface. The intermediary is discarded after fulfilling its purpose of defining the via geometry.
Solution Approach 2:
The method performs preliminary actions by first forming recesses in the wafer substrate before depositing copper. The recesses are created by removing sacrificial stacking structures in advance, preparing the substrate topology beforehand. This preliminary recess formation ensures that copper is deposited only in the intended via locations and prevents copper residue on the wafer surface.
2Reliability
If carrier substrates are used for wire bonding in stacked die structures, then electrical connections between dies can be established, but the package size increases
Solution Approach 1:
The invention transitions from two-dimensional wire bonding on a carrier substrate to three-dimensional vertical connections through the silicon substrate. By forming TSVs that penetrate the substrate vertically, electrical connections are achieved in the third dimension (depth), eliminating the need for lateral wire bonds on a large carrier substrate and enabling compact 3D IC packaging.
3Productivity
If continuous improvement in 2D integration density is pursued through lithography, then more components can be integrated, but physical limits are reached due to minimum feature size constraints
Solution Approach 1:
The patent addresses the saturation of 2D integration density by transitioning to three-dimensional integration. Through-silicon vias enable vertical stacking of functional layers and multiple dies, moving component integration from the planar (2D) domain to the vertical (3D) domain. This dimensional transition allows continued increase in effective integration density without further reduction in lateral feature sizes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of TSVs with improved efficiency and reduced copper residue, facilitating the creation of smaller, more densely packed three-dimensional integrated circuits while maintaining a compact package size.
Implementation Method 1
The recess is filled with a conductive material
Data Source
AI summary
A method of forming a semiconductor device having a through-silicon via (TSV) is provided. A semiconductor device is provided having a first dielectric layer formed thereon. One or more dielectric layers are formed over the first dielectric layer, such that each of the dielectric layers have a stacking structure, wherein the stacking structures in the one or more dielectric layers are vertically aligned. The stacking structures may be, for example, metal rings. The stacking structures are then removed to form a first recess. A second recess is formed by extending the first recess into the substrate. The second recess is filled with a conductive material to form the TSV.