Sacrificial Insulating Layers for TSV Planarization
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Solution Overview
Problem
Conventional semiconductor manufacturing processes, such as chemical mechanical polishing (CMP), are costly and inefficient for exposing conductive through silicon vias (TSV) due to the difficulty in detecting end points and achieving a uniformly planar surface, leading to issues like unopened or uneven TSV surfaces and leakage.
Innovation Solution
A method involving the use of sacrificial insulating layers with different material compositions, such as silicon nitride and silicon oxide, is employed to form TSVs, where a second insulating layer with a distinct composition is conformally or non-conformally applied over a first insulating layer, and both are partially removed using CMP to expose the conductive via, facilitating clear end point detection and planarization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If chemical mechanical polishing (CMP) is used to expose conductive TSV, then the TSV surface can be planarized, but end point detection is difficult and leakage issues occur
Solution Approach 1:
A sacrificial insulating layer is introduced as an intermediary between the conductive TSV and the overlying insulating layers. This sacrificial layer has distinct material properties that enable clear end point detection during CMP through optical or tactile sensing, while still serving the functional purpose of protecting the TSV during manufacturing. The sacrificial layer acts as a mediator that solves both the planarity requirement and the detection problem.
Solution Approach 2:
The sacrificial insulating layer is designed with material composition that provides distinct optical or physical characteristics compared to surrounding layers. This allows the CMP process to detect when the sacrificial layer is fully removed (end point) through changes in light reflection, absorption, or other measurable properties, enabling precise control without damaging the underlying conductive TSV.
2Ease of manufacture
If conventional CMP process is used for TSV exposure, then manufacturing cost is reduced, but TSV may remain unopened or broken due to lack of clear end point detection
Solution Approach 1:
The sacrificial insulating layer serves as a temporary protective structure that guides the CMP process. It allows the use of cost-effective CMP equipment and processes while ensuring reliable TSV exposure through its detectable removal. The sacrificial layer is removed after serving its protective function, leaving the TSV properly exposed without the need for expensive alternative processes.
3Ease of manufacture
If photolithographic etching with 1x stepper is used to expose TSV, then manufacturing cost is reduced, but overlay margin is insufficient
Solution Approach 1:
The sacrificial insulating layer is formed in advance during the insulating layer deposition process, before the TSV exposure step. This preliminary action establishes precise alignment references that guide subsequent etching or CMP processes, ensuring accurate TSV exposure without requiring high-cost 1x stepper equipment. The sacrificial layer's position and dimensions are predetermined with high precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the accuracy of chemical mechanical polishing by allowing for better end point detection and planarization, reducing the risk of unopened or broken TSVs and leakage issues, thereby improving the manufacturing efficiency and quality of semiconductor devices.
Implementation Method 1
removing a portion of the insulating layers to expose the conductive via
Data Source
AI summary
A semiconductor device can be formed by first providing a semiconductor wafer, and forming a conductive via into the semiconductor wafer. A portion of the semiconductor wafer can be removed so that the conductive via extends above a surface of the semiconductor wafer. A first insulating layer can be formed over the surface of the semiconductor wafer and the conductive via, followed by a second insulating layer, the second insulating layer having a different material composition than the first insulating layer. Portions of the insulating layers can be removed to expose the conductive via.