TSV Scan Chain Architecture for Low-Contact Die Stack Testing
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Solution Overview
Problem
Testing thousands of through silicon/substrate vias (TSVs) in integrated circuit die or stacks is expensive and resource-intensive, as existing methods require extensive testing resources.
Innovation Solution
A scan architecture with circuits and scan cells adapted for testing TSV paths, allowing for testing with a minimum number of contacts and using low-cost testers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional testing methods are used to test thousands of TSVs, then testing coverage is improved, but testing cost and resource requirements increase significantly
Solution Approach 1:
The patent segments the TSV testing function into two distinct phases: an initial comprehensive test performed on a subset of TSVs using conventional methods, and a subsequent selective test performed on remaining TSVs using a scan chain-based method. This segmentation allows the system to achieve complete testing coverage while reducing overall resource requirements by applying the simpler scan-based method to the majority of TSVs.
Solution Approach 2:
The patent creates a universal scan chain infrastructure that can test multiple TSVs simultaneously through a single integrated path. The scan chain serves as a multi-functional testing mechanism that can selectively access and test any TSV in the array, replacing the need for multiple separate testing resources and enabling efficient bulk testing of TSVs.
2Measurement precision
If all TSVs are tested using comprehensive methods, then testing accuracy is improved, but testing time increases
Solution Approach 1:
The patent performs preliminary comprehensive testing on a representative subset of TSVs first to establish baseline quality metrics and identify potential systematic issues. Based on the results of this preliminary test, the system then applies a faster selective testing approach to the remaining TSVs, adjusting testing parameters and thresholds based on the preliminary findings to maintain accuracy while reducing overall testing time.
Solution Approach 2:
The patent applies partial comprehensive testing (rather than full comprehensive testing to all TSVs) by performing detailed accuracy-critical tests only on a subset of TSVs, while using the faster scan-chain-based selective testing method on the remaining TSVs. This partial application of the more time-consuming comprehensive method achieves sufficient testing accuracy without the full time cost of applying it universally.
3Device complexity
If the number of test contacts is reduced, then device complexity is improved, but testing capability is worsened
Solution Approach 1:
The patent merges multiple individual TSV test paths into a single integrated scan chain structure. Instead of requiring separate test contacts and independent test paths for each TSV, the scan chain combines all TSV testing functions into one unified sequential access path, dramatically reducing the number of required test contacts while maintaining the ability to test any TSV in the array.
Solution Approach 2:
The patent transitions from a two-dimensional array of independent TSV test contacts to a one-dimensional sequential scan chain structure. By reorganizing the testing architecture along a different dimensional axis (sequential time-based access rather than parallel spatial access), the system reduces the number of simultaneous contacts required while preserving complete testing capability through systematic sequential access to all TSVs.
Data Source
AI summary
The disclosure describes a novel method and apparatus for testing different types of TSVs in a single die or different types of TSV connections in a stack of die. The testing is facilitated by test circuitry associated with each type of TSV. The test circuitry includes a scan cell adapted for testing TSVs.