TSV Scan-Chain Testing for Die-Stack Resistance Verification
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Solution Overview
Problem
Testing of through silicon/substrate vias (TSVs) in integrated circuit dies is challenging due to the need for extensive resources and high costs associated with verifying connectivity and resistance across thousands of TSVs, especially when stacking dies, as existing methods require expensive testers and complex setups.
Innovation Solution
A scan path architecture incorporating scan cells with test response, voltage reference, scan input, control inputs, and test stimulus outputs is used to test TSVs for continuity, shorts, and resistance, allowing for efficient testing by serially connecting scan cells and utilizing IEEE 1149.1 TAP to control the testing process, including switchable load resistors integrated into the die to reduce external probe requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional testing methods are used to test thousands of TSVs for connectivity and resistance, then testing coverage is improved, but testing cost and resource requirements increase significantly
Solution Approach 1:
The die is divided into multiple scan chains, each containing multiple scan cells that can independently test groups of TSVs. This segmentation allows parallel testing of multiple TSVs through separate scan chains, reducing the overall testing resources needed while maintaining comprehensive testing coverage across all TSVs in the die.
Solution Approach 2:
The scan cells are designed with multi-functionality to perform both connectivity testing and resistance testing of TSVs using the same hardware infrastructure. The scan cells can be configured to execute different test patterns that verify both the presence of conductive paths and the electrical resistance values, eliminating the need for separate dedicated testing equipment for each function.
2Reliability
If comprehensive testing of all TSVs is performed, then reliability is improved, but testing time increases
Solution Approach 1:
The scan path architecture enables continuous testing operations where test patterns are continuously shifted through scan cells and TSVs without interruption. The serial scanning mechanism allows uninterrupted sequential testing of all TSVs, maximizing the utilization of testing resources and reducing idle time between test operations, thereby completing comprehensive reliability testing more efficiently.
Solution Approach 2:
Testing is organized into periodic test cycles with different test patterns that can be systematically applied to different groups of TSVs. The scan chains can be configured to periodically test specific TSV groups with appropriate test patterns, ensuring all TSVs are thoroughly tested over multiple cycles while optimizing the overall testing schedule and reducing total testing time.
Data Source
AI summary
An integrated circuit die includes a substrate of semiconductor material having a top surface, a bottom surface, and an opening through the substrate between the top surface and the bottom surface. A through silicon via (TSV) has a conductive body in the opening, has a top contact point coupled to the body at the top surface, and has a bottom contact point coupled to the body at the bottom surface. A scan cell has a serial input, a serial output, control inputs, a voltage reference input, a response input coupled to one of the contact points, and a stimulus output coupled to the other one of the contact points.