TSV Scan Control Circuit for Stacked Memory Failure Detection
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Solution Overview
Problem
Existing memory devices with through-silicon vias (TSVs) face challenges in efficiently detecting failures, particularly in stack memory systems like high bandwidth memory (HBM), which utilize a base chip and multiple memory chips interconnected by TSVs, where data strobing signals are generated based on clock signals.
Innovation Solution
The memory device incorporates a base die and multiple core dies with scan control circuits that manage through vias, allowing for test modes where nodes are set to floating states or driven by power supply voltage, enabling identification of via failures through scan currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If scan control circuits are added to detect through-via failures, then reliability is improved, but device complexity increases
Solution Approach 1:
The scan control circuit is designed to perform multiple functions: it can detect open failures, short failures, and distinguish between normal and failed states of through-vias using the same circuit structure. The circuit responds to different test patterns (first and second test patterns) to identify various failure modes, making the detection system versatile without requiring separate dedicated circuits for each failure type.
Solution Approach 2:
The detection process is divided into multiple test modes with different test patterns. The scan control circuit processes data through different scan chains (first scan chain, second scan chain, third scan chain) with specific test patterns applied to different through-via groups. This segmentation allows systematic detection of various failure types while maintaining a unified circuit architecture.
2Measurement precision
If multiple test modes with different test patterns are implemented, then measurement precision is improved, but ease of operation deteriorates
Solution Approach 1:
The detection process uses periodic application of different test patterns in different test modes. The first test pattern is applied during one test mode to detect certain failure types, while the second test pattern is applied during another test mode to detect different failure types. This periodic switching between test patterns enables comprehensive detection while maintaining a structured, repeatable testing procedure.
Solution Approach 2:
The scan control circuit is pre-configured with multiple scan chains and test patterns before actual failure detection begins. The different test modes are prepared in advance with specific test patterns assigned to different scan chains, allowing the detection process to proceed systematically without requiring complex real-time decision-making during operation.
Data Source
AI summary
A memory device includes a base die and a plurality of core dies stacked over the base die. The base die includes a first base scan control circuit connected to a first node connected to a first through via included in a first column and a second base scan control circuit connected to a second node connected to a second through via included in a second column. The first base scan control circuit sets the first node at a floating state when the first column is selected in a test mode and drives the first node when the second column is selected during the test mode.