TSV Scan Path Architecture for Serial Resistance and Short Testing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Testing of thousands of through-silicon/substrate vias (TSVs) in integrated circuit die stacks is resource-intensive and costly due to the need for extensive testing of connectivity and resistance across numerous vertical conductive paths.
Innovation Solution
A scan path architecture incorporating scan cells that digitize response voltages against a reference and drive stimulus voltages to TSV contact points, allowing for serial testing of TSVs for continuity, shorts, and resistance using a IEEE 1149.1 Test Access Port (TAP) and switchable load resistors integrated within the die.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional testing methods are used to test thousands of TSVs, then comprehensive connectivity and resistance testing can be performed, but the testing cost and resource requirements increase significantly
Solution Approach 1:
The patent combines multiple testing functions (connectivity testing, resistance testing, and stimulus generation) into a single integrated scan path architecture. The scan cells are configured to perform both connectivity verification and resistance measurement through the same physical path, eliminating the need for separate testing equipment and reducing overall system complexity while maintaining comprehensive test coverage
Solution Approach 2:
The scan path architecture is designed to perform multiple testing functions universally. The same scan cells and test vectors are used for both connectivity testing and resistance testing, making the testing system multi-functional. This universal approach allows a single testing infrastructure to handle various TSV parameters without requiring specialized equipment for each test type
2Measurement precision
If external load resistors are used for TSV resistance testing, then accurate resistance measurements can be obtained, but the testing process requires additional external components and setup time
Solution Approach 1:
The patent implements self-service by integrating load resistors directly into the scan cell architecture within the die. The scan cells contain internal load resistors that are automatically connected during resistance testing, eliminating the need for external load resistor components. This self-contained approach simplifies the testing setup while maintaining measurement accuracy, as the internal resistors are precisely controlled and integrated into the testing pathway
Solution Approach 2:
The load resistors are nested within the scan cell structure itself. The scan cells contain the load resistors as internal components, creating a hierarchical integration where the resistance measurement functionality is embedded within the broader scan path architecture. This nesting eliminates external dependencies and simplifies the overall testing system
3Reliability
If all TSVs are tested in parallel, then testing coverage is comprehensive, but the testing time and equipment resource requirements increase
Solution Approach 1:
The patent segments the TSV testing into manageable groups using scan cells that can be configured to test specific subsets of TSVs. The scan path architecture allows division of the total TSV population into multiple testable segments, enabling systematic coverage of all TSVs while controlling the complexity and time required for each testing phase. This segmentation allows for organized testing sequences that maintain comprehensive coverage without overwhelming resource requirements
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables efficient and cost-effective testing of TSVs by reducing the need for external load resistors and allowing for serial testing of large numbers of TSVs, thereby reducing testing time and equipment costs.
Implementation Method 1
scan cells adapted for testing TSVs... that digitize response voltages against a reference
Implementation Method 2
drive stimulus voltages to TSV contact points... testing of TSVs for continuity, shorts, and resistance
Data Source
AI summary
An integrated circuit die includes a substrate of semiconductor material having a top surface, a bottom surface, and an opening through the substrate between the top surface and the bottom surface. A through silicon via (TSV) has a conductive body in the opening, has a top contact point coupled to the body at the top surface, and has a bottom contact point coupled to the body at the bottom surface. A scan cell has a serial input, a serial output, control inputs, a voltage reference input, a response input coupled to one of the contact points, and a stimulus output coupled to the other one of the contact points.