Scan-Based Test Architecture for 3D IC TSV Defect Detection
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Solution Overview
Problem
Current interconnect testing technologies for 3-D integrated circuits (ICs) face challenges in efficiently identifying and diagnosing defects in through-silicon vias (TSVs), which can lead to signal degradation, power consumption issues, and reduced yield due to imperfect etching, alignment problems, and stress-induced cracking, especially during pre-bond testing where existing probe technologies struggle to contact thousands of individual TSVs.
Innovation Solution
A scan-based test architecture is introduced, comprising a scan chain with XOR gates and a control register that shifts and stores control signals to selectively combine data from TSVs with neighboring scan cells, allowing for accurate detection and identification of single and multiple faults in TSVs by applying test stimuli and analyzing responses using walking 1/0 test patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional probe technologies are used for pre-bond testing of TSVs, then testing can be performed, but the probe card cannot make contact with thousands of individual TSVs
Solution Approach 1:
The patent segments the testing approach by dividing TSVs into groups that can be tested collectively through bonding interfaces rather than requiring individual probe contact. The bonding process itself creates testable structures where TSV defects can be detected through the bonded interface using conventional probing techniques.
Solution Approach 2:
The patent introduces bonding interfaces and intermediary structures that enable indirect access to TSVs. By using the bonding process to create testable pathways, the system mediates between the unaccessible TSVs and the probe card, allowing defect detection without direct TSV probing.
2Productivity
If TSV-based interconnects are used in 3-D ICs, then bandwidth increases by a factor of eight and power consumption reduces by half, but manufacturing precision deteriorates due to imperfect etching, alignment problems, and stress-induced cracking
Solution Approach 1:
The patent performs testing during the bonding process itself, before final assembly completion. By integrating test capabilities into the bonding workflow, defects can be detected early when TSVs are still accessible through bonding interfaces, allowing for preliminary identification of manufacturing issues before they propagate through the final product.
Solution Approach 2:
The patent implements feedback mechanisms where test results from bonding interfaces inform subsequent processing decisions. Defect detection during bonding provides immediate feedback that can trigger rework, replacement, or adjustment of affected TSVs or bonding structures, closing the loop between manufacturing and quality control.
3Reliability
If TSVs are tested individually before bonding, then defect identification is possible, but testing time increases and yield reduces due to the need to test thousands of individual TSVs
Solution Approach 1:
The patent merges multiple TSV testing operations into a single integrated process that occurs during bonding. Instead of testing thousands of TSVs individually before bonding, the approach combines TSV testing with the bonding process itself, allowing simultaneous testing of multiple TSVs through the bonding interface and dramatically reducing total test time.
Solution Approach 2:
The patent creates a universal testing approach where the bonding interface serves dual purposes: both joining TSVs and enabling defect detection. This multi-functional use of the bonding process eliminates the need for separate dedicated TSV testing equipment and procedures, streamlining the overall manufacturing workflow.
Data Source
AI summary
Aspects of the invention relate to scan-based test architecture for interconnects in stacked designs. The disclosed scan-based test architecture comprises a scan chain. Scan cells on the scan chain are configured to receive data from, based on bits of a control signal, outputs of neighboring scan cells or outputs of mixing devices that combine data from through-silicon vias with data from the outputs of the neighboring scan cells. The scan-based test architecture can be used to identify single or multiple defective through-silicon vias.