Parallelized Checkpointing Using TSVs and Segmented Memory Mats
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Solution Overview
Problem
Existing memory module architectures lack efficient parallelized check pointing capabilities, which are essential for fault tolerance in computing systems, particularly in systems utilizing stacked memory with heterogeneous or homogeneous memory dies.
Innovation Solution
The implementation of a system and method for parallelized check pointing using Dual In-line Memory Modules (DIMMs) with vertically integrated memory dies, employing Through Silicon Vias (TSVs) and an address generator circuit to facilitate simultaneous data transfer across multiple memory dies, enabling heterogeneous or homogeneous memory architectures to achieve parallel data reading and writing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional memory module architectures are used, then device complexity is reduced, but check pointing speed and efficiency deteriorate
Solution Approach 1:
The memory die is divided into multiple independent mats (e.g., mat0-mat7), each capable of autonomous parallel operation. Each mat contains its own address generator, TSV controller, and data transfer mechanisms, enabling simultaneous check pointing operations across multiple memory regions without interference, thus achieving high-speed parallelized check pointing.
Solution Approach 2:
The patent transitions from traditional two-dimensional memory organization to a three-dimensional stacked memory architecture using Through-Silicon Vias (TSVs). Multiple memory dies are stacked vertically, with TSVs providing vertical interconnects between layers. This dimensional change enables parallel data transfer paths through the stack, dramatically increasing check pointing throughput while maintaining manageable complexity through modular die design.
2Productivity
If multiple mats transfer data simultaneously, then productivity is improved, but device complexity increases
Solution Approach 1:
Each mat is equipped with autonomous control logic including address generators and TSV controllers that independently manage data transfer operations. The mats self-coordinate through shared control signals without requiring complex external arbitration, enabling high-productivity parallel transfers while keeping the control architecture manageable through distributed intelligence.
Solution Approach 2:
Address generators in each mat pre-generate address sequences for parallel access to multiple memory locations simultaneously. This preliminary address preparation enables coordinated data transfer across multiple mats without real-time address calculation overhead, increasing productivity while simplifying control logic through pre-computed access patterns.
3Productivity
If stacked memory with TSVs is implemented, then check pointing efficiency is improved, but manufacturing precision requirements increase
Solution Approach 1:
The stacked memory is divided into multiple discrete dies, each containing complete or partial memory functionality. This segmentation allows independent manufacturing and testing of individual dies before stacking, reducing the overall manufacturing precision burden. TSV alignment requirements are managed at the die-to-die interface level rather than requiring perfect precision across the entire memory stack.
Solution Approach 2:
The patent employs TSV technologies with optimized dimensional parameters and materials that balance manufacturing feasibility with performance requirements. By carefully selecting TSV diameter, spacing, and depth parameters, the design achieves high check pointing efficiency while remaining compatible with current manufacturing precision capabilities. Parameter optimization allows efficient parallel data transfer through TSVs without requiring unrealistic precision levels.
Data Source
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AI summary
A system and method that includes a memory die, residing on a stacked memory, which is organized into a plurality of mats that include data. The system and method also includes an additional memory die, residing on the stacked memory, that is organized into an additional plurality of mats and connected to the memory die by a Through Silicon Vias (TSVs), the data to be transmitted along the TSVs.