TSV Test Circuit With Self-Calibration for Capacitance Measurement
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Solution Overview
Problem
Existing methods fail to accurately measure parasitic capacitances of Through Silicon Vias (TSVs) in semiconductor chips, which affect signal quality in memory devices like High Bandwidth Memory (HBM), due to variations in manufacturing and complex signal paths.
Innovation Solution
A test circuit configuration is implemented, comprising a switch circuit, reference resistor, constant current source, and control circuit, which performs calibration and measurement operations to accurately determine parasitic capacitance by utilizing a single pad electrode and accounting for manufacturing variations and self-capacitance of the test circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional measurement method is used, then the measurement process is simple, but the measurement precision of parasitic capacitance is insufficient due to manufacturing variations and complex signal paths
Solution Approach 1:
The test circuit performs self-calibration by measuring and storing the self-capacitance of the test circuit itself before actual measurements. This preliminary action compensates for manufacturing variations and circuit parasitics, enabling high-precision measurements without requiring multiple pad electrodes or complex external calibration equipment.
Solution Approach 2:
The test circuit measures its own self-capacitance and uses this information to compensate for manufacturing variations and parasitic effects during actual TSV capacitance measurements. This self-service approach eliminates the need for external calibration equipment and multiple pad electrodes, achieving high precision while maintaining circuit simplicity.
2Measurement precision
If multiple pad electrodes are used for measurement, then the measurement precision improves, but the device complexity and manufacturing difficulty increase
Solution Approach 1:
The invention extracts and measures only the essential self-capacitance parameter of the test circuit itself, storing this value for later compensation during actual measurements. This extraction approach eliminates the need for multiple pad electrodes and complex external calibration equipment, achieving high precision with a single pad electrode and simplified manufacturing.
3Measurement precision
If manufacturing variations are not accounted for, then the device complexity remains low, but the measurement precision deteriorates due to variations in TSV parasitic capacitance
Solution Approach 1:
The test circuit incorporates feedback by measuring its own self-capacitance and using this information to compensate for manufacturing variations during actual TSV capacitance measurements. This feedback mechanism enables high-precision measurements while maintaining a relatively simple circuit structure, as the compensation is performed automatically within the same test circuit.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables precise measurement of parasitic capacitance of TSVs, improving signal quality by accounting for manufacturing variations and self-capacitance, allowing for accurate assessment of the entire signal path and individual TSVs without requiring multiple pad electrodes.
Implementation Method 1
a first level of the output voltage appearing at the pad electrode in a first calibration operation, in which the switch circuit is in a first state in which the pad electrode is connected to the constant current source
Implementation Method 2
a switch circuit, configured to connect the pad electrode to either one of a constant current source and a test circuit according to a control signal
Data Source
AI summary
Disclosed herein is an apparatus that includes a first semiconductor chip, and a first TSV penetrating the first semiconductor chip. The first semiconductor chip includes a first resistor coupled between a first power supply and a first node, a switch circuit coupled between the first node and the first TSV, a pad electrode operatively coupled to the first node, and a constant current source operatively coupled to either one of the first node and the pad electrode.