Through-Silicon Via Self-Testing Semiconductor Integrated Circuit
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Solution Overview
Problem
Conventional semiconductor integrated circuits face inefficiencies in testing and repair due to defects in through-silicon vias, leading to increased test time, reduced fabrication yield, and the need for external apparatus and memory for defect detection and repair.
Innovation Solution
A semiconductor integrated circuit design that enables self-testing and repair by generating and transmitting test pulse signals through vias, allowing for the identification of defective vias and rerouting signals to repair paths within the circuit, thereby reducing test and repair times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If external apparatus and memory are used to test and repair vias, then defect detection capability is improved, but test time and data storage requirements increase
Solution Approach 1:
The patent implements self-service by enabling the semiconductor integrated circuit to perform its own testing and repair operations. Test pulse signals are generated internally within the circuit, propagated through the vias, and the results are evaluated by the circuit itself without requiring external testing apparatus. This eliminates the need for external memory to store test data and significantly reduces test time while maintaining defect detection capability.
2Measurement precision
If external apparatus is used to observe test signals, then test accuracy is improved, but device complexity and available test channels are reduced
Solution Approach 1:
The patent extracts the testing function from external apparatus and relocates it within the semiconductor integrated circuit itself. By generating test pulse signals internally and using internal circuitry to evaluate the results, the system eliminates the need for complex external testing equipment and memory systems, thereby reducing overall device complexity while maintaining test accuracy.
3Reliability
If repair operations are performed using conventional methods, then defective vias can be identified, but fabrication yield is reduced due to additional repair time
Solution Approach 1:
The patent implements preliminary action by performing the repair operation immediately after defect detection within the same testing cycle. The circuit automatically switches signal paths to bypass defective vias based on the test results, eliminating the need for separate repair processing steps. This integration of detection and repair operations significantly reduces total processing time and improves fabrication yield while maintaining reliable defect identification.
Data Source
AI summary
A semiconductor integrated circuit includes a plurality of semiconductor chips coupled to one another through vias, wherein a lowermost semiconductor chip of the plurality of semiconductor chips is configured to generate a first test pulse signal and transmit the first test pulse signal through the via, an uppermost semiconductor chip of the plurality of semiconductor chips is configured to generate a second test pulse signal while substantially maintaining a time difference with the first test pulse signal, and to transmit the second test pulse signal through the via, and the plurality of semiconductor chips are configured to generate test result signals for determining whether the vias are defective in response to the first test pulse signal and the second test pulse signal.