Semiconductor Package With Through Silicon Via Chip Stack
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Solution Overview
Problem
Current semiconductor packaging technologies face challenges in achieving high-speed and high-density integration while maintaining design reliability and process efficiency, particularly in the integration of small-sized and lightweight electronic products.
Innovation Solution
A semiconductor package design that includes a substrate with a chip stack portion featuring multiple semiconductor chips connected via through silicon vias (TSVs) and an internal sealing member, allowing for flip-chip type installation and efficient electrical connectivity, along with additional sealing members for protection and stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple semiconductor chips are integrated in a compact stack structure, then packaging density is improved, but manufacturing precision requirements increase due to the need for precise alignment and connection through TSVs
Solution Approach 1:
The patent implements a chip stack structure where multiple semiconductor chips are vertically stacked and interconnected through through-silicon vias (TSVs). This nesting arrangement achieves high packaging density by utilizing the vertical dimension, with chips positioned at different height levels and connected through conductive TSVs that penetrate the substrate, effectively creating a nested three-dimensional integration architecture.
Solution Approach 2:
The patent transitions from traditional planar two-dimensional chip arrangement to three-dimensional vertical stacking. By utilizing the vertical dimension and implementing chips at different height levels connected through TSVs, the design achieves higher integration density while managing the increased manufacturing precision requirements through specialized alignment structures and processes.
2Speed
If chips are connected through TSVs in a vertical stack, then signal transmission speed is improved, but device complexity increases due to the multi-layer interconnection structure
Solution Approach 1:
The patent employs vertical three-dimensional stacking with TSVs to create direct signal pathways between chips at different height levels. This vertical interconnection approach reduces signal transmission distance and improves speed compared to lateral connections, while the standardized TSV structure and integration process help manage the inherent device complexity.
Solution Approach 2:
The patent divides the semiconductor system into discrete chip modules stacked vertically, with each chip containing specific functional elements. The TSVs provide dedicated interconnection channels between these segmented chips, allowing independent optimization of each chip while achieving high-speed communication through the vertical stack architecture.
3Reliability
If internal sealing members are used to fill spaces between chips, then reliability is improved through better protection, but manufacturing complexity increases due to additional sealing processes
Solution Approach 1:
The patent incorporates internal sealing members that extend along the lateral surfaces of chips within the stack, filling the spaces between adjacent chips. This nested sealing approach provides mechanical support, environmental protection, and stress distribution for the interconnected chips, enhancing reliability while integrating the sealing function within the existing stack structure.
Solution Approach 2:
The internal sealing members serve multiple functions simultaneously: they fill voids between chips, provide mechanical support and alignment, protect against environmental contaminants, and distribute thermal and mechanical stresses. This multi-functionality improves reliability across multiple aspects while avoiding the need for separate dedicated sealing structures or processes.
Data Source
AI summary
A semiconductor package including a substrate, a chip stack portion disposed on the substrate and including a plurality of first semiconductor chips, at least one second semiconductor chip disposed on the chip stack portion, and a signal transmitting medium to electrically connect the at least one second semiconductor chip and the substrate to each other, such that the chip stack portion is a parallelepiped structure including a first chip that is a semiconductor chip of the plurality of first semiconductor chips and includes a through silicon via (TSV), a second chip that is another semiconductor chip of the plurality of first semiconductor chips and electrically connected to the first chip through the TSV, and an internal sealing member to fill a space between the first chip and the second chip.