Through-Silicon Vias for Semiconductor Die Connectivity
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Solution Overview
Problem
The complexity and size limitations of semiconductor devices are exacerbated by the need for numerous contact pads and additional metallization layers, leading to increased resistivity, power consumption, and production costs due to routing congestion and high resistive vias.
Innovation Solution
The implementation of through-silicon vias (TSVs) that route signal, power, and ground connections from the back side of a semiconductor die, reducing the need for contact pads and upper metallization layers by directly connecting circuitry to the substrate's second side, thereby minimizing resistive paths and allowing for fewer metallization layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If contact pads are bunched together along the outside periphery to provide signal, power, and ground connectivity, then connectivity is achieved, but device size reduction is limited due to routing congestion
Solution Approach 1:
The patent moves contact pads from the traditional top surface periphery to the back side of the semiconductor device, utilizing the third dimension (depth/vertical stacking) to resolve the routing congestion problem. This allows signal, power, and ground connections to be established without constraining the top surface area, enabling device size reduction while maintaining connectivity.
Solution Approach 2:
Instead of placing contact pads on the top surface as is conventional, the patent inverts the approach by locating contact pads on the back side of the device. This inversion of the traditional contact pad location eliminates routing congestion on the top surface and enables more efficient use of device area.
2Device complexity
If additional metallization layers are added to handle increased routing complexity, then more interconnects are available, but resistivity and power consumption increase due to extra high resistive vias
Solution Approach 1:
The patent extracts power and ground routing functions from the upper metallization layers by implementing a power mesh structure in the lower metallization layers. This separation allows the upper layers to focus on signal routing while lower layers handle power distribution, reducing the need for additional high resistive vias and decreasing power consumption.
Solution Approach 2:
The patent segments the metallization layers into distinct functional groups: lower layers dedicated to power and ground distribution, and upper layers dedicated to signal routing. This segmentation reduces routing complexity and minimizes the number of vias required, thereby reducing resistivity and power loss.
3Reliability
If the two upper most metallization layers are dedicated to power and ground routing in a power mesh, then power distribution is improved, but signal routing capacity is reduced
Solution Approach 1:
The patent segments metallization layers by function, placing power and ground routing in lower metallization layers with a power mesh structure, while dedicating upper metallization layers to signal routing. This segmentation ensures reliable power distribution without compromising signal routing capacity.
Solution Approach 2:
The patent applies different routing strategies to different parts of the device: power and ground connections utilize a power mesh structure in lower layers where high current carrying capacity is needed, while signal routing utilizes the upper layers where low inductance and high speed are critical. This local optimization of routing quality improves both power distribution and signal integrity.
Data Source
AI summary
A system and method for making semiconductor die connections with through-substrate vias are disclosed. Through substrate vias are formed through the substrate to allow for signal connections as well as power and ground connections. In one embodiment the substrate has an interior region and a periphery region surrounding the interior region. A first set of through substrate vias are located within the periphery region, and a second set of through substrate vias are located within the interior region, wherein the second set of through substrate vias are part of a power matrix. The second set of through substrate vias bisect the substrate into a first part and a second part.