Semiconductor Die Package With TSV Interconnects
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Solution Overview
Problem
Current 3D-integrated circuit packaging technologies face challenges in achieving high interconnect density and cost-effectiveness, particularly in package-on-package solutions, due to limitations in through-package interconnect pitch and thermal coupling, as well as the expense of interposer technology.
Innovation Solution
The solution involves embedding a logic die in a mold material with a redistribution layer and incorporating Through Substrate Vias (TSVs) and lateral connecting devices, allowing for independent testing of the logic die and reducing the need for expensive interposer technology by enabling overlap placement of the second die, thus reducing overall package size and interconnect length.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional PoP approach with separate BGA packages is used, then packaging flexibility is maintained, but package height becomes problematic and interconnect density is insufficient
Solution Approach 1:
The patent transitions from 2D side-by-side die placement to 3D vertical stacking with overlapping projections. The first and second dies are positioned at different vertical levels with their projections overlapping, enabling high-density interconnects through vertical through-substrate vias while reducing the horizontal footprint and overall package height compared to traditional PoP approaches.
Solution Approach 2:
The patent embeds the second die within the vertical projection of the first die, creating a nested configuration where the second die is positioned inside the bounding box of the first die when viewed from above. This nesting approach maximizes space utilization and enables dense interconnect routing through the substrate.
2Quantity of substance
If FO-WLP with laser-drilled TPVs is used, then through-package interconnects are achieved, but TPV pitch is limited to several 100 μm
Solution Approach 1:
The patent replaces laser drilling with mechanical punching or drilling methods to create through-substrate vias. This substitution enables achieving much finer via pitches (e.g., 40 μm or less) that are not attainable with laser drilling, thereby enabling high-density interconnects required for Wide I/O standards while maintaining cost-effectiveness.
Solution Approach 2:
The patent changes the via formation method from laser drilling to mechanical punching/drilling, which fundamentally alters the achievable via pitch parameter. This parameter change enables transitioning from 100 μm class TPV pitch to 40 μm or finer pitch, satisfying the requirements for high-bandwidth memory interfaces.
3Quantity of substance
If direct stacking with TSVs in logic die is used, then high interconnect density is achieved, but thermal coupling between dies becomes high
Solution Approach 1:
The patent introduces a substrate as an intermediary layer between the first and second dies. This substrate provides through-substrate via interconnects while acting as a thermal management interface, allowing control over thermal coupling between dies. The substrate material and via configuration can be optimized to manage heat flow independently of the electrical interconnect function.
4Quantity of substance
If silicon interposer is used, then high density interconnects are achieved, but package construction becomes expensive
Solution Approach 1:
The patent replaces expensive silicon interposer technology with a cost-effective organic or laminate substrate. This substrate, while less technologically advanced than silicon interposers, provides sufficient performance for the application at a much lower cost, enabling high-density interconnects without the prohibitive manufacturing expenses of silicon-based solutions.
Solution Approach 2:
The patent changes the substrate material parameter from silicon to organic/laminate materials. This material substitution dramatically reduces manufacturing cost while maintaining the ability to achieve high interconnect density through appropriately configured through-substrate vias, making the solution economically viable for mass production.
5Area of stationary object
If wafer-level CSP is used, then package size is reduced, but independent packaging and testing of logic die is not allowed
Solution Approach 1:
The patent structures the package in modular segments where the first die can be independently packaged, tested, and validated before final assembly with the second die. The substrate and interconnect structure are designed to accommodate this sequential process, allowing independent handling and testing of the logic die while maintaining the compact wafer-level package footprint.
Data Source
Figure 1
Figure 2a~2d
Figure 2e~2h
AI summary
The present invention is related to a package comprising a first die (1) embedded in a reconstructed wafer (2) obtainable by the known FO-WLP or eWLB technologies. In addition to the first die, a Through Substrate Via insert (16) is embedded in the wafer, the TSV insert being a separate element, possibly a silicon die with metal filled vias (17) interconnecting contacts on the front (12) and back (11) sides of the insert. A second die (15) is mounted on the back side of the substrate (2), with contacts (8) on the second die in electrical connection with the TSV insert's contacts (11) on the back side of the substrate. On the front side of the substrate, a lateral connecting device (18) is mounted which interconnects the TSV insert's contacts (12) on the front side of the substrate to contacts (7) on the front side of the first die. The lateral connecting device (18) and the TSV insert (16) thereby effectively interconnect the contacts on the first (1) and second (15) dies. Preferably the lateral connecting device is mounted on a redistribution layer (3) on the front side of the substrate, as it is known from FO-WLP technology.