Through-Silicon Via Interconnect for Semiconductor Die Stacking
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Solution Overview
Problem
Conventional semiconductor packages with stacked dies require thick spacers and conductive wires for electrical connection, leading to increased thickness, electrical resistance, and power consumption due to longer interconnection lines.
Innovation Solution
The use of through-silicon vias (TSVs) for electrical interconnection between semiconductor dies, eliminating the need for conductive wires, and the formation of redistribution layers and solder balls for external connections, which reduces package size and improves electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conductive wires are used to electrically connect semiconductor dies to substrate or to each other, then electrical connection is achieved, but the overall length of interconnection lines increases leading to increased electrical resistance and power consumption
Solution Approach 1:
The patent transitions from planar wire-based interconnection to three-dimensional vertical interconnection through through-silicon vias (TSVs). Conductive pathways are formed by penetrating vertically through the semiconductor substrate, enabling direct electrical connection between stacked dies without requiring long lateral wire paths. This dimensional change from 2D to 3D interconnection dramatically reduces interconnection length and associated resistance.
Solution Approach 2:
The patent extracts and eliminates the conductive wire interconnection layer from the package structure by implementing direct TSV-based electrical connection. The wire bonding or wire-based interconnect architecture is removed entirely, replacing it with vertically integrated conductive pathways formed through the substrate itself, thereby eliminating the source of increased resistance and power consumption.
2Ease of operation
If thick spacers are formed to position conductive wires between stacked semiconductor dies, then proper positioning is achieved, but the overall thickness of the unit package increases
Solution Approach 1:
The patent extracts and eliminates the thick spacer structure from the package architecture by implementing direct TSV-based interconnection. Without conductive wires requiring lateral positioning, the spacer layer becomes unnecessary and is removed entirely. This extraction of the spacer component directly reduces the overall package thickness while maintaining proper die alignment through alternative means.
Solution Approach 2:
The patent moves from lateral wire positioning requiring vertical spacers to vertical TSV-based connection where positioning is achieved through precise via alignment and bonding pad registration. The positioning function transitions from being accomplished by thick vertical spacers to being accomplished by precise lateral alignment features and bonding interfaces, eliminating the need for thickness-increasing spacer structures.
3Reliability
If conductive wires are used as interconnection lines, then electrical connection is established, but processing speed is reduced and power consumption increases
Solution Approach 1:
The patent implements vertical three-dimensional interconnection through TSVs, replacing lateral wire-based connection. This dimensional transition creates much shorter electrical pathways between stacked dies, reducing signal propagation distance and time. The vertical integration enables faster signal transmission and processing speeds while maintaining reliable electrical connection between dies.
Solution Approach 2:
The patent fundamentally changes the interconnection architecture from wire-based to TSV-based, altering key parameters including interconnection length, resistance, and inductance. The TSV structure provides lower resistance and inductance pathways compared to conventional wires, enabling faster signal transmission and improved processing speed while maintaining electrical connection reliability.
Data Source
AI summary
Semiconductor devices are disclosed. In an embodiment, a plurality of second semiconductor dies formed with through-silicon vias are stacked on a first semiconductor die. The stack of the second semiconductor dies is encapsulated by an encapsulant. Redistribution layers are formed on one surface of the stack and are connected to the through-silicon vias. Solder balls are attached to the respective redistribution layers. In another embodiment, a plurality of second semiconductor dies formed with through-silicon vias are stacked on a first semiconductor die formed with through-silicon vias. Redistribution layers are formed on the back surface of the first semiconductor die. Solder balls are attached to the respective redistribution layers. Further disclosed are methods for fabricating the semiconductor devices.