TSV Semiconductor Package for Modular Assembly and Yield Improvement
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Solution Overview
Problem
The challenge in packaging multiple semiconductor dies within a single device is that the entire device must be assembled before burn-in and testing can occur, leading to reduced yield rates due to faulty components, and once assembled, individual dies cannot be replaced or substituted to meet varying customer demands for different processor-memory combinations.
Innovation Solution
A semiconductor through-silicon via (TSV) device package is fabricated with a logic die that can undergo separate burn-in and testing, allowing for the attachment of another tested logic die package, improving yield and enabling flexible assembly based on demand by allowing individual processors and memory to be stocked and combined as needed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple semiconductor dies are packaged within a single device before testing, then the device can be assembled early for production efficiency, but yield rates decrease due to faulty components and individual dies cannot be replaced later
Solution Approach 1:
The patent divides the semiconductor device into separate packageable units (bottom logic die package and top logic die package) that can be tested and validated independently before final assembly. This segmentation allows each component to be quality-checked separately, improving yield rates while maintaining production efficiency through parallel processing of multiple discrete packages.
2Ease of manufacture
If the entire device is assembled before testing, then production flow is simplified, but individual dies cannot be substituted to meet varying customer demands
Solution Approach 1:
The patent performs preliminary packaging and testing of individual logic dies separately before final device assembly. This preliminary action creates pre-validated, standardized packages that can be stored and later combined in different configurations to meet specific customer demands, thereby maintaining production simplicity while enabling post-manufacturing adaptability.
3Reliability
If individual dies are packaged separately for later assembly, then yield improves and flexibility increases, but device complexity increases due to multiple packaging steps
Solution Approach 1:
The patent creates universal, standardized logic die packages with consistent interfaces and mounting configurations that can be used across different device types and customer requirements. This universality allows the same packaged components to serve multiple functions and be assembled into various final device configurations, reducing the need for multiple specialized packaging processes despite the benefits of separate packaging.
Data Source
AI summary
A first package includes a laminate layer, an overmold layer above and in direct contact with the laminate layer, and a logic circuit-through-silicon via (TSV) layer including a first logic die and TSVs. The logic circuit-TSV layer is within the overmold layer, and the TSVs are electrically exposed at a top surface of the overmold layer. The first package may be fabricated and tested by a first party prior to being provided to a second party. A second package includes a second logic die. The second party may attach the second package to the first package at the electrically exposed TSVs of the first package to realize a complete and functional semiconductor device.