Through-Silicon Via Semiconductor Package Structure
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Solution Overview
Problem
Conventional Ball Grid Array (BGA) semiconductor package structures face limitations in electrical performance during high-frequency or high-speed operations due to lengthy wire paths and require multiple connection interfaces, leading to increased fabrication costs and reduced wiring layout space when embedding large semiconductor chips.
Innovation Solution
A package structure with a core board featuring through-silicon vias that electrically connect electrode pads on both surfaces of a semiconductor chip, eliminating the need for conductive through holes and optimizing wiring layout by preventing the inactive surface of the chip from occupying substrate space.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the inactive surface of the semiconductor chip is disposed on the first substrate to embed the chip, then the chip is securely positioned in the through cavity, but the wiring layout space of the first substrate and second substrate is occupied and reduced
Solution Approach 1:
The patent utilizes through-silicon vias to extend the wiring path from the active surface electrode pads through the chip thickness to the inactive surface electrode pads. This three-dimensional wiring approach allows electrical connections to be established without occupying additional planar wiring layout space on the substrates, effectively moving the wiring problem from a two-dimensional surface constraint to a three-dimensional volume solution.
Solution Approach 2:
The inactive surface of the semiconductor chip serves dual functions: it provides mechanical support and structural stability for chip embedding in the through cavity, while also serving as an electrical connection interface through the through-silicon vias that connect to electrode pads on both the active and inactive surfaces. This multi-functionality eliminates the need for separate wiring layers on the substrates.
2Reliability
If conductive through holes are used to connect the semiconductor chip to two edges of the package structure, then electrical connection is achieved, but the circuit path is lengthened which deteriorates electrical quality
Solution Approach 1:
Instead of extending conductive through holes from the substrates to the chip edges as in conventional designs, the patent inverts the approach by creating through-silicon vias within the chip itself that connect electrode pads on opposite surfaces. This internal chip-level connection approach dramatically shortens the circuit path compared to external substrate-level connections, as the vias traverse only the chip thickness rather than the entire package depth.
3Productivity
If multiple connection interfaces are used in conventional BGA package structure, then high pin number is achieved, but fabrication costs increase
Solution Approach 1:
The patent merges multiple connection interfaces into a unified through-silicon via structure. Instead of separately implementing wire bonding, flip-chip connections, and solder ball implantation as in conventional BGA packages, the invention combines these functions into integrated through-silicon vias that provide both mechanical support and electrical connection in a single fabrication process, thereby reducing manufacturing steps and costs while maintaining high pin count capability.
Data Source
AI summary
Disclosed is a package structure including a semiconductor chip disposed in a core board having a first surface and an opposite second surface. The package structure further includes a plurality of first and second electrode pads disposed on an active surface and an opposite inactive surface of the semiconductor chip respectively, the semiconductor chip having a plurality of through-silicon vias for electrically connecting the first and second electrode pads. As a result, the semiconductor chip is electrically connected to the two sides of the package structure via the through-silicon vias instead of conductive through holes, so as to enhance electrical quality and prevent the inactive surface of the semiconductor chip from occupying wiring layout space of the second surface of the core board to thereby increase wiring layout density and enhance electrical performance.