TSV Semiconductor Device With Two-Dimensional Die Offset
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Solution Overview
Problem
Conventional semiconductor devices with through silicon vias (TSV) stacked in a single direction result in a large wasted keep-out area due to the stepped offset, limiting the integration of additional components at the edge of the die stack.
Innovation Solution
The semiconductor dies are stacked with a two-dimensional offset in orthogonal directions, reducing the overall stepped offset and unused keep-out area by forming TSVs that connect corresponding die bond pads across multiple levels, allowing for more efficient use of the die stack's surface area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If die are stacked with a stepped offset in one direction to enable TSV access to bond pads, then electrical connectivity between die levels is achieved, but a large keep-out area is wasted at the stepped edge where no components can be built
Solution Approach 1:
The patent transitions from one-dimensional offset stacking to two-dimensional offset stacking. By introducing offsets in both x and y directions, the design creates a more compact arrangement where the keep-out areas of multiple die levels overlap more effectively, reducing the total wasted area while maintaining TSV access to bond pads at all levels.
Solution Approach 2:
The patent merges the offset functions in both x and y directions into a unified two-dimensional offset scheme. This combines the keep-out area reductions from both dimensional offsets, creating a synergistic effect that maximizes the usable area of the die stack while preserving electrical connectivity through TSVs.
2Ease of manufacture
If conventional one-dimensional offset stacking is used, then manufacturing process is simpler, but the overall device area is larger due to excessive keep-out area
Solution Approach 1:
The patent extends the offset concept from one dimension to two dimensions, creating a more space-efficient die stack arrangement. The two-dimensional offset pattern allows die to be positioned such that keep-out areas overlap more effectively, reducing the bounding box area of the entire stack while maintaining manufacturability through standardized TSV processes.
3Area of stationary object
If two-dimensional offset stacking is implemented, then keep-out area is reduced by approximately 50%, but the alignment precision requirement increases
Solution Approach 1:
The patent segments the offset arrangement into discrete, repeatable patterns in both x and y directions. By defining specific offset distances along each axis, the complex two-dimensional arrangement becomes a series of manageable, modular positioning steps that can be executed with standard manufacturing tolerances, reducing the overall alignment precision burden.
Solution Approach 2:
The patent applies different offset values along the x and y axes, optimizing the keep-out area reduction for each direction independently. This localized optimization allows the design to achieve maximum area efficiency while accommodating the specific capabilities and tolerances of the manufacturing process in each dimensional direction.
Data Source
AI summary
A semiconductor device is disclosed including semiconductor dies stacked with an offset in two orthogonal directions. TSVs may then be formed connecting corresponding die bond pads on respective dies in the stack. By offsetting the dies in two orthogonal directions, the overall stepped offset, and consequently the size of the unused keep-out area of the stack, is reduced.