TSV-Stacked SERDES Blocks for High-Speed 3D Chip Packaging

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Solution Overview

Problem

Conventional stacked die packaging using wirebond is unsuitable for high-speed SER/DES applications due to inductance and capacitance issues, limiting its suitability for high-density and compact 3D chip packaging, especially in applications where size and thermal performance are critical.

Innovation Solution

The use of Through Silicon Via (TSV) within the SER/DES block to connect dice vertically, eliminating the need for wirebonds and spacers, and enabling efficient routing and alignment of chips through redistribution layers, allowing for high-speed data transfer and improved thermal management.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If wirebond technology is used to connect stacked dice, then ease of manufacture is improved, but inductance and capacitance increase making it unsuitable for high-speed SER/DES applications

Engineering Contradiction:

Improveease of manufactureVSAvoidelectrical performance

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

The patent replaces wirebond mechanical connection with Through-Silicon-Via (TSV) technology, substituting a mechanical wire-bonding system with a direct silicon-via connection system. This eliminates the wirebond inductance and capacitance issues while maintaining manufacturing feasibility through established TSV fabrication processes.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent introduces Through-Silicon-Vias as an intermediary connection structure between stacked dice. These TSVs act as mediators that provide direct electrical pathways through the substrate, replacing the wirebond intermediary and reducing parasitic effects while enabling high-speed signal transmission.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Device complexity

If conventional stacked die packaging is used, then device complexity is reduced, but thermal performance deteriorates due to inadequate heat dissipation

Engineering Contradiction:

Improvedevice complexityVSAvoidthermal performance

Core Design Contradiction:

Device complexityVSTemperature

Solution Approach 1:

The patent applies local quality by creating thermally conductive pathways specifically in regions where heat generation occurs. The TSV structure provides localized thermal management capability, directing heat away from hot spots in the SER/DES block while maintaining simple overall device architecture.

Inventive Principle:

Principle #3Local quality

3Ease of manufacture

If spacer materials are used in stacked die packaging, then ease of manufacture is improved, but device volume increases reducing packaging density

Engineering Contradiction:

Improveease of manufactureVSAvoidpackage volume

Core Design Contradiction:

Ease of manufactureVSVolume of moving object

Solution Approach 1:

The patent extracts and eliminates the spacer material from the stacked die packaging structure. By removing this unnecessary component and using TSV-based direct connection, the invention reduces package volume and increases density while maintaining manufacturing simplicity through direct die-to-die bonding.

Inventive Principle:

Principle #2Taking out (Extraction)

4Ease of manufacture

If wirebonds are used for connection, then ease of manufacture is improved, but inductance increases limiting high-speed data transfer capability

Engineering Contradiction:

Improveease of manufactureVSAvoiddata transfer speed

Core Design Contradiction:

Ease of manufactureVSSpeed

Solution Approach 1:

The patent replaces the wirebond mechanical connection system with a TSV-based direct silicon connection system. This substitution eliminates the long wirebond paths that create inductance, enabling high-speed data transfer while keeping the manufacturing process accessible through standard semiconductor fabrication techniques.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS11894342B2Stacking integrated circuits containing serializer and deserializer blocks using through

Publication Date: 2024.02.06 BROADPAK CORP

AI summary

Methods and systems for stacking multiple chips with high speed serializer/deserializer blocks are presented. These methods make use of Through Via (TV) to connect the dice to each other, and to the external pads. The methods enable efficient multilayer stacking that simplifies design and manufacturing, and at the same time, ensure high speed operation of serializer/deserializer blocks, using the TVs.