Two-Section TSV Side Wall Structure for Notch Prevention
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Solution Overview
Problem
The manufacturing process of through silicon vias (TSVs) in semiconductor packaging faces challenges in controlling the etching depth, leading to incomplete or over-etched through holes, which can result in open circuits or electrical leakages due to notch formation at the interface between the substrate and the metal-oxide semiconductor layer.
Innovation Solution
A semiconductor structure and manufacturing method involving a substrate with a through hole formed by alternating etching conditions to create a two-section side wall structure, where the first side wall portion has regular scallops and the second side wall portion is non-scalloped, allowing precise control of the etching depth and preventing notch formation, enabling proper deposition of an insulating liner layer and ensuring electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the etching process is performed to form a through hole penetrating the substrate, then electrical connection between top and bottom surfaces is achieved, but the etching depth cannot be precisely controlled leading to incomplete or over-etched holes
Solution Approach 1:
The etching process is divided into two distinct stages: a first etching stage that creates a through hole with a first depth, and a second etching stage that extends the hole to a greater second depth. This segmentation allows precise control over the etching depth by separating the formation of the conductive post cavity from the final through-hole creation, preventing both incomplete etching and over-etching.
Solution Approach 2:
A conductive post is formed in the through hole before completing the etching process to the final depth. This preliminary action of forming the conductive post at an intermediate stage allows subsequent insulation and device formation to proceed without risking damage from excessive etching, while still enabling final electrical connection.
2Productivity
If the through hole is over-etched, then complete penetration is achieved, but notches are formed at the substrate interface causing electrical leakages
Solution Approach 1:
The conductive post is formed in the through hole before completing the etching to full penetration. This preliminary formation of the conductive structure allows the etching process to proceed to complete penetration without risking damage to the substrate interface, as the conductive post is already in place to establish the electrical connection pathway.
Solution Approach 2:
An insulating layer is deposited between the conductive post and the substrate interface. This insulating intermediary prevents electrical leakages at the sensitive substrate interface while allowing the through hole to be completely formed, thus maintaining both productivity and electrical insulation reliability.
3Strength
If the through hole is not completely etched, then substrate integrity is maintained, but wires cannot be exposed for connection
Solution Approach 1:
The etching process is segmented into stages, with the first stage creating a through hole of sufficient depth to expose wires for connection, and a second stage completing the penetration. This segmentation ensures wires are exposed and connected in the first stage, maintaining substrate integrity, while the second stage achieves complete penetration for final connection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents notches and ensures a continuous insulating liner layer, enhancing the reliability and manufacturing yield of semiconductor structures by maintaining electrical insulation and connectivity between the conductive post and the substrate.
Implementation Method 1
a through hole is required to be formed on a wafer during the manufacture of the TSV. For example, the required through hole for forming the TSV may be achieved by an etching process on the back side of the wafer
Implementation Method 2
the deposition thickness of the insulting liner layer on the notches may be insufficient or the insulting liner layer may be non-continuous on the notches
Data Source
AI summary
A semiconductor structure and a manufacturing method thereof are provided. The semiconductor structure includes a substrate, a device layer and a least one conductive post. The substrate includes a first surface, a second surface opposite to the first surface, and at least one through hole penetrating the substrate. The substrate includes a first side wall portion and a second side wall portion at the through hole. The first side wall portion is connected to the first surface and includes a plurality of first scallops. The second side wall portion is connected to the second surface and includes a non-scalloped surface. The device layer is disposed on the second surface, and the second side wall portion of the substrate further extends into the device layer along the non-scalloped surface. The conductive post is disposed in the through hole, wherein the conductive post is electrically connected to the device layer.