TSV Sidewall Contact Without Under Bump Metal
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Solution Overview
Problem
The increased use of under bump metal (UBM) in 2.5D and 3D semiconductor packages leads to higher manufacturing costs and potential degradation of chip performance due to the complexity of electrical interconnections in Through Silicon Via (TSV) structures.
Innovation Solution
A semiconductor device with a TSV structure where the sidewall of the TSV is directly connected to a conductive pad without UBM on the upper and lower surfaces, and an isolation structure is formed only in the substrate to surround the TSV, eliminating the need for UBM and ensuring electrical isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the amount of under bump metal (UBM) is increased to improve electrical connection in TSV structures, then the electrical connection quality is improved, but the process cost increases and chip performance may be degraded
Solution Approach 1:
The patent removes the under bump metal (UBM) layer from the TSV structure, extracting this problematic component that caused both cost increase and performance degradation. The TSV is designed to directly contact the conductive pad without UBM, simplifying the structure while maintaining electrical connection quality through optimized direct contact geometry and material selection.
Solution Approach 2:
The patent changes the electrical connection parameters by eliminating the UBM layer and modifying the TSV geometry and material composition. By adjusting the TSV diameter, depth, and contact area with the conductive pad, the patent achieves reliable electrical connection without requiring UBM, thus reducing process complexity and cost.
2Reliability
If UBM is used to ensure electrical connection between TSV and conductive pad, then connection reliability is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent extracts and eliminates the UBM layer from the manufacturing process, reducing the number of deposition and patterning steps required. The simplified structure allows for fewer process layers and reduced manufacturing complexity while maintaining connection reliability through direct TSV-to-pad contact.
Solution Approach 2:
The patent merges the electrical connection function directly between the TSV and conductive pad by eliminating the intermediate UBM layer. This consolidation simplifies the manufacturing process by reducing the number of distinct layers and process steps while achieving the same electrical connection objective more efficiently.
3Reliability
If isolation structure is extended into the dielectric layer to improve electrical isolation, then isolation effectiveness is improved, but device complexity and process steps increase
Solution Approach 1:
The patent applies isolation structures selectively only in the substrate region where electrical isolation is most critical, rather than extending them through the entire dielectric layer. This localized approach provides sufficient isolation effectiveness while minimizing added structural complexity and process steps in the upper dielectric regions.
Solution Approach 2:
The patent segments the isolation function by confining the isolation structure to specific regions (substrate level) rather than applying it uniformly throughout the entire device structure. This segmentation allows electrical isolation to be achieved where needed without unnecessarily increasing overall device complexity or requiring additional process steps in non-critical areas.
Data Source
AI summary
A semiconductor device includes at least one wafer and at least one TSV (through silicon via) structure. The at least one wafer each includes a substrate, an isolation structure, and a conductive pad. The isolation structure is formed in the substrate and extends from a first side of the substrate toward a second side opposite to the first side of the substrate. The conductive pad is formed at a dielectric layer disposed on the first side of the substrate, wherein the conductive pad is electrically connected to an active area in the substrate. The at least one TSV structure penetrates the at least one wafer. The conductive pad contacts a sidewall of the at least one TSV structure, and electrically connects the at least one TSV structure and the active area in the substrate. The isolation structure separates from and surrounds the at least one TSV structure.