Semiconductor Chip TSV Sidewall Pad Interconnect
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Solution Overview
Problem
Existing multi-chip semiconductor devices face challenges with wire-bonding, such as large form factor and poor electrical performance due to long wire interconnects, and through-silicon-via (TSV) technologies struggle to efficiently handle both common and non-common signals, leading to increased die size and cost, as well as potential failure rates.
Innovation Solution
The implementation of through-silicon-vias for common signals and sidewall pads for non-common signals, using a flexible sidewall substrate with polymer layers and copper interconnects, allows for efficient signal routing without requiring changes to existing wafer designs, accommodating both types of signals and reducing manufacturing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire-bonding is used to connect stacked chips, then electrical connections between chips are established, but the form factor becomes large and electrical performance deteriorates due to long wire interconnects
Solution Approach 1:
The patent transitions from planar wire-bonding connections to vertical through-silicon-via connections, changing the dimensional approach of interconnect routing. By routing signals vertically through the silicon substrate rather than laterally through wires, the patent achieves shorter connection paths and improved electrical performance while reducing the horizontal form factor.
Solution Approach 2:
The patent extracts the interconnection function from external wire-bonds and integrates it directly into the silicon substrate through TSVs. This consolidation eliminates the need for separate wire interconnects, reducing both the form factor and improving electrical performance by removing the lateral routing path.
2Reliability
If through-silicon-vias are used to handle both common and non-common signals, then electrical connections are established, but die size increases and manufacturing complexity increases
Solution Approach 1:
The patent segments the signal routing function by creating separate TSVs for common signals and separate sidewall pads for non-common signals. This segmentation allows each type of signal to be routed through optimized paths, reducing the overall die size required compared to a unified TSV approach that would need to accommodate all signal types.
Solution Approach 2:
The patent applies different interconnection structures to different signal types: TSVs are used where vertical routing is optimal for common signals, while sidewall pads are used for non-common signals requiring lateral access. This local optimization reduces the total die size by placing each interconnection type where it is most efficient.
3Reliability
If through-silicon-vias are used for signal routing, then electrical connections are established, but manufacturing cost increases and failure rate increases
Solution Approach 1:
The patent segments the interconnection approach to use TSVs only where necessary for common signals, while using simpler sidewall pad structures for non-common signals. This segmentation reduces the total number of complex TSV operations required, thereby lowering manufacturing cost and potential failure rates associated with TSV fabrication.
4Ease of manufacture
If existing wafer designs are used with TSV technology, then manufacturing is simplified, but efficient handling of both common and non-common signals is not achieved
Solution Approach 1:
The patent segments the signal handling approach by maintaining existing wafer designs for common signals while adding sidewall pad structures for non-common signals. This segmentation allows the patent to preserve manufacturing simplicity for the core TSV process while adding enhanced functionality for lateral signal routing without requiring complete redesign of the wafer fabrication process.
Data Source
AI summary
Subject matter disclosed herein may relate to packaging for multi-chip semiconductor devices as may be used, for example, in flash memory devices. In an example embodiment, a semiconductor chip may comprise a through-silicon via and a sidewall pad.