TSV Blind Hole Sidewall Planarization for Low-Leakage Semiconductor Structures

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Solution Overview

Problem

The Bosch etching process for Through Silicon Via (TSV) technology results in rough sidewalls, leading to interface cracking and leakage issues due to excessive substrate consumption and size deviations during the oxidation process.

Innovation Solution

A method involving the formation of a sacrificial layer on the sidewall of a blind hole, where a reaction source gas reacts with the layer and substrate to form a second sacrificial layer with varying thickness, reducing the roughness by shortening the distance between convex and concave portions, thereby minimizing substrate consumption and size deviations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If Bosch etching process is used to form TSV, then manufacturing efficiency is improved, but sidewall roughness increases causing interface cracking and leakage

Engineering Contradiction:
Improvemanufacturing efficiencyVSAvoidsidewall roughness
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

A planarization layer is formed on the sidewall of the blind hole before filling with conductive material. This preliminary action smooths the rough sidewall surface created by Bosch etching, preventing interface cracking and leakage while maintaining the manufacturing efficiency of the Bosch process.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The planarization layer acts as an intermediary between the rough sidewall and the conductive material. It mediates the interface by providing a smooth surface that prevents direct contact between the conductive material and the scalloped sidewall, thereby eliminating interface cracking and leakage issues.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Manufacturing precision

If oxidation process is performed to remove roughness, then sidewall smoothness is improved, but substrate consumption increases causing size deviation

Engineering Contradiction:
Improvesidewall smoothnessVSAvoidsubstrate consumption
Core Design Contradiction:
Manufacturing precisionVSLoss of substance

Solution Approach 1:

The planarization layer serves as a sacrificial intermediary that is deposited on the sidewall and then selectively removed. It provides the necessary smoothness during processing but is completely removed afterward, preventing substrate consumption and size deviation while achieving sidewall smoothness.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The planarization layer is a temporary, disposable structure used only during the manufacturing process. It is formed to smooth the sidewall, performs its function, and then is completely removed. This approach avoids permanent substrate consumption while achieving the desired smoothness temporarily during critical processing steps.

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

3Manufacturing precision

If multiple planarization processes are performed, then sidewall roughness is reduced, but manufacturing complexity increases

Engineering Contradiction:
Improvesidewall roughnessVSAvoidmanufacturing complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The planarization layer is formed as a single preliminary action before conductive material filling. This one-time formation step smooths the sidewall surface, eliminating the need for multiple iterative planarization processes and reducing manufacturing complexity while achieving the desired roughness reduction.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method effectively reduces sidewall roughness, improves interface integrity, and enhances the yield of semiconductor structures by preventing excessive substrate consumption and size deviations, thus reducing leakage current and ensuring the integrity of the semiconductor structure.

Implementation Method 1

A reaction source gas is provided, such that the reaction source gas reacts with the first sacrificial layer and a portion of the substrate at the sidewall of the blind hole to form a second sacrificial layer

Methodology Applied
Scientific EffectChemical reaction: Chemical Bonding

Data Source

PatentUS12046478B2Semiconductor structure and method for manufacturing semiconductor structure
Publication Date: 2024.07.23 CHANGXIN MEMORY TECH INC
  • US12046478B2 patent drawing
  • US12046478B2 patent drawing
  • US12046478B2 patent drawing

AI summary

A method for manufacturing a semiconductor structure includes: a substrate is provided; the substrate is etched to form a blind hole, a sidewall of the blind hole has a first roughness; at least one planarization process is performed on the sidewall of the blind hole until the sidewall of the blind hole has a preset roughness less than the first roughness. The planarization process includes: a first sacrificial layer is formed on the sidewall of the blind hole; a reaction source gas is provided such that the reaction source gas reacts with the first sacrificial layer and a portion of the substrate at the sidewall of the blind hole to form a second sacrificial layer; and the second sacrificial layer is removed, and after the second sacrificial layer is removed, the sidewall of the blind hole has a second roughness less than the first roughness.