Through Silicon Via Packaging Using Silicon Germanium Substrates
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Solution Overview
Problem
Existing three-dimensional packaging techniques using through silicon via (TSV) structures face challenges in achieving thin silicon substrate thickness due to stress effects from chemical mechanical polishing (CMP) processes, leading to increased complexity and production costs.
Innovation Solution
A method involving a silicon germanium substrate with a thickness of 50 μm to 750 μm, where a second silicon substrate is formed using epitaxial growth or CVD processes, allowing for precise control of TSV depth and reducing production costs through gas or wet etching processes that minimize stress and damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of stationary object
If chemical mechanical polishing (CMP) process is used to back grind the silicon substrate, then the silicon substrate can be thinned, but stress effect is generated on the silicon substrate causing the thickness cannot be very small (at least 200 μm)
Solution Approach 1:
The patent changes the material parameter of the substrate from pure silicon to silicon germanium alloy, which has different mechanical properties. This material parameter change allows the substrate to be thinned below 200 μm without generating harmful stress effects, as the alloy composition can be optimized to reduce internal stress while maintaining structural integrity.
Solution Approach 2:
The patent employs composite material structure by forming a silicon germanium substrate that combines silicon and germanium elements. This composite approach leverages the beneficial properties of both materials: silicon provides semiconductor functionality while germanium reduces stress effects during thinning processes, enabling thinner substrates with improved reliability.
2Ease of manufacture
If the silicon substrate thickness is reduced to below 200 μm, then the TSV depth is reduced and production cost is decreased, but the CMP process cannot achieve this thinness without stress effects
Solution Approach 1:
By changing the substrate material composition to silicon germanium alloy with specific germanium content, the patent enables new thickness ranges to be achieved. The altered material parameters allow thinning processes to reach below 200 μm without the stress limitations of pure silicon, thereby reducing TSV depth and associated manufacturing costs.
Solution Approach 2:
The patent replaces the conventional CMP mechanical polishing process with alternative thinning approaches that work effectively on silicon germanium substrates. The material substitution enables the use of different thinning mechanisms that are less prone to generating stress effects, facilitating cost-effective production of thinner substrates.
3Reliability
If deep TSV structure is formed with depth of at least 200 μm, then the silicon substrate thickness is sufficient, but the process complexity and production cost are increased
Solution Approach 1:
The patent changes the substrate material to silicon germanium, which modifies the etching characteristics and mechanical properties. This parameter change allows for shallower TSV depths to achieve the same functional equivalence, thereby simplifying the TSV formation process and reducing overall device complexity while maintaining structural stability.
Solution Approach 2:
Instead of forming deep TSVs in thick substrates to ensure stability, the patent inverts the approach by using material composition optimization to enable thinner substrates with shallower TSVs. This inverted strategy achieves stability through material properties rather than through increased geometric dimensions, reducing process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables a thinner TSV structure with reduced production costs and minimal sidewall damage, enhancing integration density and reducing signal delay issues in semiconductor packaging.
Implementation Method 1
removing the second type substrate using a gas etching process or a wet etching process
Implementation Method 2
removing the second type substrate using a gas etching process or a wet etching process
Implementation Method 3
forming a second silicon substrate different from the first type of substrate on the first type substrate
Implementation Method 4
forming a second silicon substrate different from the first type of substrate on the first type substrate
Data Source
AI summary
A method is provided for fabricating a through silicon via packaging structure. The method includes providing a first type substrate, and forming a second type substrate deferent from the first type substrate on the first type substrate. The method also includes forming a semiconductor device on a first surface of the second type substrate, and forming an interlayer dielectric layer on the first surface of the second type substrate. Further, the method includes forming a metal interconnection structure in the interlayer dielectric layer, and forming a through silicon via structure perforating the second type substrate and electrically connecting with the metal interconnection structure. Further, the method also includes removing the first type substrate using a gas etching process or a wet etching process to expose a second surface of the second type substrate and a bottom surface of the through silicon via structure.