TSV Solder Reflow for 3D Packaging Void Reduction
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Solution Overview
Problem
Current Through Silicon Via (TSV) technology in semiconductor packaging is complex and costly, requiring advanced processing and support structures, which hinders simplification, yield improvement, and cost reduction.
Innovation Solution
A method involving the formation of tapered vias in silicon dies, filled with conductive material using a mask layer and reflow process to create via and surface contacts, allowing for simplified stacking and elimination of under bump metallization, using solder for connections which reduces void formation and eliminates the need for temporary carriers during stacking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional TSV process with copper filling and under bump metallization is used, then connection reliability is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent extracts and eliminates the under bump metallization (UBM) layer from the traditional TSV process. By using solder paste directly filled into the TSV holes and reflowing to form spherical solder contacts, the complex multi-layer metallization structure (copper TSV + UBM + solder bump) is simplified to a single-step solder filling process, reducing manufacturing steps while maintaining connection reliability
Solution Approach 2:
The patent merges the TSV filling and bump formation steps into a single reflow process. The solder paste is applied to the die surface, and during reflow, it simultaneously fills the TSV holes and forms spherical surface contacts, eliminating the need for separate UBM deposition and bump formation steps
2Reliability
If traditional TSV process with multiple processing steps is used, then connection quality is improved, but manufacturing cost and time increase
Solution Approach 1:
The patent applies solder paste to the die surface before the reflow process, pre-positioning the conductive material in a controlled manner. This preliminary application ensures proper material distribution and prevents defects during the subsequent reflow step, enabling faster processing while maintaining connection quality
Solution Approach 2:
The patent utilizes the phase transition of solder paste from solid/semi-solid state to liquid state during reflow heating, and then back to solid state upon cooling. This phase change enables the solder to automatically fill the TSV holes and form spherical surface contacts in a single thermal cycle, significantly reducing processing steps and time while ensuring reliable connections
3Productivity
If simplified solder filling process is used, then manufacturing cost and time are reduced, but void formation may increase
Solution Approach 1:
The patent applies solder paste with specific local properties (viscosity, particle size distribution, flux composition) optimized for TSV filling. The paste formulation is tailored to ensure proper wetting and filling behavior during reflow, preventing void formation while maintaining the simplified single-step process
Solution Approach 2:
The reflow process naturally forms spherical solder contacts on the die surface and fills TSV holes with rounded menisci. This spherical geometry minimizes trapped air pockets and promotes complete filling, reducing void formation while maintaining manufacturing efficiency
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the TSV process, reduces costs, and enhances throughput by using solder for connections, which are faster to form and less prone to voids, and eliminates the need for temporary carriers, thus improving the efficiency and reliability of 3D chip packaging.
Implementation Method 1
The method includes reflowing to at least partially fill the vias and contact openings to form via contacts in the vias and surface contacts in the mask openings
Data Source
AI summary
A method for preparing a die for packaging is disclosed. A die having first and second major surfaces is provided. Vias and a mask layer are formed on the first major surface of the die. The mask includes mask openings that expose the vias. The mask openings are filled with a conductive material. The method includes reflowing to at least partially fill the vias and contact openings to form via contacts in the vias and surface contacts in the mask openings.