TSV Fault-Tolerant Circuit With Spare Via Switching in 3D ICs
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Solution Overview
Problem
Existing 3D IC technologies face challenges with defective or malfunctioning through-silicon vias (TSVs), where a single defective TSV can render the entire 3D IC non-functional, and current methods lack effective solutions for fault tolerance.
Innovation Solution
The integration of a TSV fault-tolerant circuit in ICs, which includes operational TSVs, a spare TSV, and fault-tolerance control modules coupled with a decoder, allowing for the deactivation of defective TSVs and activation of spare TSVs based on positioning codes to ensure continuous signal transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If TSV-based 3D IC technology is used to achieve shorter interconnects and lower power consumption, then performance and power efficiency are improved, but the risk of defective TSVs increases due to fabrication and bonding limitations
Solution Approach 1:
The patent implements preliminary action by incorporating a fault-tolerance control module and decoder that can proactively detect and switch away from defective TSVs before they cause complete system failure. The system pre-establishes alternative signal paths and control logic to handle potential TSV defects, allowing the 3D IC to maintain reliability while using TSV-based interconnects for lower power consumption.
Solution Approach 2:
The patent applies parameter changes by dynamically altering the operational state of TSVs based on their health status. The fault-tolerance control module monitors TSV performance parameters and can switch between operational and standby TSVs, changing the system's configuration to maintain functionality despite individual TSV failures, thus resolving the reliability concern while preserving the power benefits of TSV technology.
2Ease of manufacture
If traditional planar IC interconnects are used, then manufacturing is simpler, but interconnect length is longer resulting in higher latency and power consumption
Solution Approach 1:
The patent applies dimensionality change by transitioning from traditional planar (2D) IC interconnects to three-dimensional (3D) stacked architecture with vertical through-silicon vias. This moves the interconnect path from a long lateral route to a short vertical path through the silicon substrate, dramatically reducing signal transmission latency while maintaining ease of manufacture through established TSV fabrication processes.
3Reliability
If spare TSVs and fault-tolerance control modules are added to achieve fault tolerance, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent uses an intermediary approach by introducing a fault-tolerance control module that acts as a mediator between the TSVs and the rest of the circuit. This control module, along with the decoder, provides intelligent routing and switching capabilities that manage the complexity of having multiple TSVs (including spare ones) while maintaining system reliability. The intermediary structure organizes the complexity in a manageable way rather than creating uncontrolled circuit complexity.
Data Source
AI summary
An integrated circuit with a through-silicon via (TSV) fault-tolerant circuit, a TSV fault tolerance method are disclosed. The IC may include a plurality of operational TSVs, a spare TSV, a plurality of fault-tolerance control modules each coupled to one of the plurality of operational TSVs and the spare TSV, and a decoder coupled to the fault-tolerance control modules. The fault-tolerance control modules may be configured to deactivate an operational TSV that is determined to be defective and activate the spare TSV based on a positioning code for the defective operational TSV from the decoder. The IC may reduce the defect rate in the fabrication of TSV-based three-dimensional (3D) IC chips.