Through-Silicon Via Stack Package with Surface Contact Metal Lines
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Solution Overview
Problem
Conventional stack packages using metal wires suffer from slow operation speeds, degraded electrical characteristics, increased size, and misalignment issues due to the use of metal wires for electrical connections, while through-silicon via stack packages face challenges with precise alignment and increased thickness due to the small surface area of projecting vias.
Innovation Solution
A through-silicon via stack package design where metal lines on the upper and lower surfaces of each semiconductor chip contact opposite halves of the via, allowing for precise stacking and reduced thickness, with the lines formed of materials like copper, aluminum, or gold, and connected via solder for improved electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If metal wires are used for electrical connections in stack packages, then electrical connections can be established between chips and substrate, but the operation speed becomes slow and electrical characteristics are degraded
Solution Approach 1:
The patent replaces the mechanical wire bonding system with an electrical conduction system through through-silicon vias. Instead of using metal wires that require physical bonding and create inductive effects, the invention creates direct electrical pathways through the silicon substrate, eliminating the mechanical connection component and its associated electrical degradation.
Solution Approach 2:
The invention extracts and removes the metal wire bonding layer from the electrical connection path. By eliminating the wire bonding interface and replacing it with through-silicon via conduction, the harmful inductive effects and resistance introduced by wire bonds are completely removed from the electrical signal path.
2Reliability
If metal wires are used for electrical connections, then connections can be formed, but additional area is needed in the substrate and the overall size of the stack package increases
Solution Approach 1:
The patent transitions from a planar wire bonding approach to a vertical through-silicon via approach. Instead of routing wires across the substrate surface requiring lateral area, the invention conducts electrical connections through the vertical dimension of the silicon substrate, eliminating the need for additional substrate area to accommodate wire routing.
3Reliability
If through-silicon vias are used with small surface area projecting portions, then electrical characteristics are improved, but precise alignment becomes difficult and the thickness of the stack package increases
Solution Approach 1:
The patent performs preliminary formation of metal lines on both the upper and lower surfaces of the silicon substrate before stacking. These pre-formed metal lines serve as alignment guides and contact surfaces that facilitate precise alignment during the stacking process, eliminating the alignment difficulties associated with small projecting via portions.
Solution Approach 2:
The invention divides the electrical connection structure into multiple segments: through-silicon vias for vertical conduction, upper surface metal lines for top chip connection, and lower surface metal lines for bottom chip connection. This segmentation allows each component to be optimized independently while working together to achieve both precise alignment and excellent electrical characteristics.
4Volume of moving object
If through-silicon vias with small surface area are used, then chip miniaturization is enabled, but the thickness of the stack package increases due to projecting portions and metal lines
Solution Approach 1:
The patent nests the metal lines within the same lateral footprint as the through-silicon vias. The upper and lower surface metal lines are positioned directly above and below the vias, creating a compact nested structure that minimizes the overall package thickness while maintaining miniaturized chip dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enables precise alignment and reduced thickness of the stack package, forming excellent electrical connections through surface contact, thereby increasing manufacturing yield and operational speed.
Implementation Method 1
connected via solder for improved electrical connections
Data Source
AI summary
A through-silicon via stack package contains package units. Each package unit includes a semiconductor chip; a through-silicon via formed in the semiconductor chip; a first metal line formed on an upper surface and contacting a portion of a top surface of the through-silicon via; and a second metal line formed on a lower surface of the semiconductor chip and contacting a second portion of a lower surface of the through-silicon via. When package units are stacked, the second metal line formed on the lower surface of the top package unit and the first metal line formed on the upper surface of the bottom package unit are brought into contact with the upper surface of the through-silicon via of the bottom package unit and the lower surface of the through-silicon via of the top package unit, respectively. The stack package is lightweight and compact, and can form excellent electrical connections.