Through Silicon Plug Stacked Chip Package Ultrasonic Bonding
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Solution Overview
Problem
The high cost and complexity of manufacturing three-dimensional semiconductor devices using through silicon vias (TSVs) for stacked chip packages, which increases the risk and uncertainty in implementation, making them expensive and limiting their adoption in cost-sensitive markets.
Innovation Solution
A semiconductor package structure and manufacturing method that utilizes ultrasonic bonding and through silicon plugs to electrically interconnect vertically stacked chips with a substrate unit, incorporating test pads for process control and redundancy, and employing sealing layers to protect electrical interconnects, thereby simplifying the assembly process and reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If through silicon vias (TSVs) are used to create three-dimensional semiconductor devices with stacked chips, then integration level and form factor reduction are improved, but manufacturing cost and complexity increase
Solution Approach 1:
The patent employs cost-effective materials and processes for TSV formation and chip stacking, using standard semiconductor manufacturing techniques rather than expensive specialized processes. This allows high integration to be achieved while controlling manufacturing costs through the use of readily available, shorter-lived process materials and methods.
Solution Approach 2:
The manufacturing process is divided into distinct modular stages: TSV formation on wafers, wafer bonding, singulation, and final packaging. This segmentation allows each step to be optimized independently and enables existing manufacturing infrastructure to be utilized, reducing overall complexity despite the advanced integration level.
2Reliability
If through silicon vias (TSVs) are used for stacked chip packages, then electrical connection efficiency is improved, but manufacturing cost increases
Solution Approach 1:
Multiple TSV formation processes are combined into a single wafer-level operation, where through-silicon vias are created, filled with conductive material, and planarized all before chip stacking. This merging reduces the number of expensive specialized process steps required and allows use of standard manufacturing equipment.
Solution Approach 2:
The patent optimizes TSV dimensions, conductive fill material composition, and bonding parameters to achieve reliable electrical connections at lower costs. By carefully controlling via diameter, depth, and fill material properties, the manufacturing cost is reduced while maintaining high electrical connection efficiency.
3Ease of operation
If wire bonding is used for electrical connections between stacked chips and substrate, then ease of assembly is improved, but signal quality deteriorates due to parasitic inductance
Solution Approach 1:
The patent extracts and eliminates the wire bonding step from the assembly process by directly integrating TSVs through the substrate and chips. This removal of the wire bonding infrastructure completely eliminates parasitic inductance while maintaining ease of assembly through automated TSV alignment and bonding processes.
4Area of stationary object
If multiple chips are stacked vertically with TSPs, then footprint reduction is improved, but manufacturing yield uncertainty increases
Solution Approach 1:
TSVs are formed and tested on wafers before chip stacking, and wafer-level electrical testing is performed to identify and isolate defective chips. This preliminary action ensures that only good chips are stacked together, maintaining high manufacturing yield while achieving dense vertical integration that reduces footprint.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces manufacturing costs and complexity, improves yield, and enhances signal quality by eliminating parasitic inductance, making TSV-based stacked packages more viable for cost-sensitive markets while maintaining high performance.
Implementation Method 1
the chips are vertically stacked and electrically interconnected by through silicon plugs to a substrate unit using ultrasonic bonding methods
Data Source
AI summary
Semiconductor package structures and methods for manufacturing the same are provided. The semiconductor package structure comprises a substrate unit and a first chip stack structure. The substrate unit comprises a circuit structure having test pads. The first chip stack structure comprises chips, and each of the chips has a plurality of through silicon plugs. The through silicon plugs of two adjacent chips are electrically connected and further electrically connected to the test pads of the substrate unit for electrical testing. Another semiconductor package structure provided by the present invention comprises a first semiconductor chip and a second semiconductor chip. Each of the semiconductor chips has test pads for electrical testing and a plurality of through silicon plugs connecting to the test pads. The second semiconductor chip is mounted on the first semiconductor chip, and a portion of the through silicon plugs of two semiconductor chips are electrically connected with each other.