TSV Stacked Semiconductor Chips Shared I/O Circuits
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Solution Overview
Problem
In semiconductor devices with TSV structures, the increasing number of pins required for high-speed interfaces, such as DDR, leads to larger chip sizes due to the need for more input/output circuits and wider I/O buses, which complicates the stacking and reduces the density of integration.
Innovation Solution
The semiconductor device is designed with a stacked configuration where each chip has TSV array portions for input/output operations and pass-through operations, allowing shared use of input/output circuits and control circuits across multiple chips, reducing the number and area of these components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the number of pins is increased to support high-speed interfaces such as DDR, then the data transmission speed is improved, but the chip size becomes larger due to the need for more input/output circuits and wider I/O buses
Solution Approach 1:
The patent divides the memory system into multiple stacked chips, each handling a portion of the data transmission. By segmenting the memory capacity across multiple chips connected via TSVs, the system achieves high-speed DDR interfaces without requiring all I/O circuits to be on a single large chip, thus distributing the area requirement across multiple smaller chips.
Solution Approach 2:
The patent transitions from a two-dimensional chip layout to a three-dimensional stacked architecture using through-silicon vias (TSVs). This vertical stacking enables high-density interconnections without increasing the planar chip area, allowing high-speed data transmission with compact chip dimensions by utilizing the vertical dimension for additional I/O capacity.
2Adaptability or versatility
If more input/output circuits are provided to support increased pins, then the interface capability is improved, but the area occupied by these circuits increases
Solution Approach 1:
The patent implements a unified I/O circuit design that serves multiple stacked chips simultaneously. The I/O circuits on each chip are designed to handle both local memory operations and inter-chip communication, enabling the same circuitry to perform multiple functions across different chips in the stack, thereby reducing the total I/O circuit area required.
Solution Approach 2:
The patent combines the I/O circuit functions of multiple chips into a coordinated system where adjacent chips share common I/O resources. By merging the control and data pathways through the TSV interconnections, the system achieves high interface capability without duplicating full I/O circuitry on each chip, thus reducing the overall area requirement.
3Productivity
If the I/O bus width is increased to support more pins, then the data throughput is improved, but the chip area becomes larger
Solution Approach 1:
The patent achieves wide effective I/O bus width by stacking multiple chips vertically with TSV interconnections. Each chip in the stack contributes to the overall data throughput, effectively creating a multi-lane parallel interface without requiring a proportionally wide bus on each individual chip. This vertical multiplication of I/O capacity maintains compact chip area while achieving high data throughput.
Solution Approach 2:
The patent segments the high-speed data interface into multiple parallel channels distributed across stacked chips. Instead of implementing a single ultra-wide I/O bus on one chip, the system divides the data throughput requirement into multiple narrower channels that are distributed across multiple chips, reducing the area burden on each individual chip while maintaining aggregate high throughput.
Data Source
AI summary
The present invention is applicable to a semiconductor device having a plurality of chips being stacked with a TSV structure in which adjacent ones of the chips are connected to each other via a plurality of through electrodes. Each of the chips includes a plurality of TSV array portions provided so as to correspond to a plurality of channels. The TSV array portions include a TSV array portion that contributes to an input and an output depending upon the number of the chips being stacked, and a pass-through TSV array portion that is not connected to an input/output circuit.