TSV Stacked Semiconductor Die Logic Distribution and Identification
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Solution Overview
Problem
Existing semiconductor chip stacking technologies using Through-Silicon-Via (TSV) interconnections do not effectively distribute logical functions over multiple dies, leading to inefficiencies in die identification and sparing, which are crucial for optimizing performance and packaging density.
Innovation Solution
A method and circuit that implement die stacking by distributing logic across multiple dies, utilizing exclusive OR (XOR) or shift register logic for die identification and storing spare die information in fuses coupled to sparing logic on a master semiconductor device, allowing for efficient die sparing and logical function distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional two-dimensional packaging techniques are used for stacked dies, then die identification and control become simpler, but packaging density and interconnection efficiency deteriorate
Solution Approach 1:
The patent transitions from conventional two-dimensional packaging to three-dimensional stacked die architecture using Through-Silicon-Via (TSV) interconnections. Multiple dies are vertically stacked and interconnected through TSVs, enabling higher packaging density by utilizing the vertical dimension rather than expanding horizontally. This dimensional transition resolves the contradiction by achieving greater packaging density while managing identification complexity through systematic addressing schemes.
2Adaptability or versatility
If dedicated TSVs are added for sending commands to specific dies, then die selection capability is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent implements a universal command bus structure where TSVs serve multiple functions: data transmission, command signaling, and die selection. Instead of dedicating separate TSVs for each function, the same interconnection infrastructure handles multiple tasks through protocol-based communication. This multi-functional approach improves die selection capability while avoiding the manufacturing complexity of dedicated TSVs for each function.
Solution Approach 2:
The patent introduces an intermediary addressing mechanism that mediates between the controller and individual dies. Rather than requiring direct dedicated connections, the system uses address-based routing through the TSV network, where the intermediary addressing logic routes commands to the appropriate die. This intermediary approach provides flexible die selection without the manufacturing burden of dedicated physical connections for each die.
3Measurement precision
If laser fuse arrangements are used for die selection, then die identification precision is improved, but process complexity and manufacturing cost increase
Solution Approach 1:
The patent extracts the die identification function from complex physical modification mechanisms like laser fuses and implements it through logical addressing schemes. Instead of physically altering dies to identify them, the system uses software-based address assignment and routing logic. This extraction of the identification function from physical modification reduces process complexity while maintaining precise die identification through logical addressing.
4Productivity
If logical functions are concentrated on single dies, then device complexity is reduced, but performance and functional distribution capability deteriorate
Solution Approach 1:
The patent segments logical functions across multiple stacked dies rather than concentrating them on a single die. Different functional blocks are distributed to different dies in the stack, with each die handling specific functions. The TSV interconnections provide high-speed communication between segmented functional blocks, enabling parallel operation and improved overall performance. This segmentation resolves the contradiction by distributing functions to enhance performance while using systematic interconnection to manage the resulting complexity.
Data Source
AI summary
A method and circuit for implementing die stacking to distribute a logical function over multiple dies, die identification and sparing in through-silicon-via stacked semiconductor devices, and a design structure on which the subject circuit resides are provided. Each die in the die stack includes predefined functional logic for implementing a respective predefined function. The respective predefined function is executed in each respective die and a respective functional result is provided to an adjacent die in the die stack. Each die in the die stack includes logic for providing die identification. An operational die signature is formed by combining a plurality of selected signals on each die. A die signature is coupled to a next level adjacent die using TSV interconnections where it is combined with that die signature.