TSV Stacked Semiconductor Package for Stress-Managed Reliability
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Solution Overview
Problem
Current semiconductor packages face challenges in achieving high integration, high-speed performance, and structural reliability while being compact and lightweight, particularly in stacked semiconductor chip configurations.
Innovation Solution
A semiconductor package design featuring stacked semiconductor chips with through silicon vias (TSVs) and bonding pads, surrounded by a chip bonding insulation layer, along with a stress reduction member and a support dummy substrate for enhanced structural reliability and heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor chips are stacked to achieve high integration, then the integration level and processing speed are improved, but the structural reliability and stress distribution deteriorate
Solution Approach 1:
The patent divides the semiconductor substrate into multiple stacked chips (first semiconductor chip, second semiconductor chip, etc.) with intermediate layers between them. This segmentation allows each chip to be processed and bonded separately, improving integration while managing stress through the layered structure. The through-silicon vias are also segmented across multiple bonding interfaces rather than spanning the entire stack height.
Solution Approach 2:
The patent introduces a stress reduction member with specific material properties (different thermal expansion coefficient) placed at the inactive surface of the first semiconductor chip. This local modification addresses stress concentration issues specifically at the bonding interface without affecting the overall chip performance. The chip bonding insulation layer also provides localized stress distribution improvement at critical bonding regions.
Solution Approach 3:
The patent employs composite material structures including the stress reduction member made of material with different thermal expansion properties, the chip bonding insulation layer combining insulating and stress-distributing properties, and the through-silicon via structure combining conductive and mechanical support functions. These composite structures resolve the contradiction between high integration and structural reliability.
2Speed
If through silicon vias are used for vertical interconnection, then the processing speed and bandwidth are improved, but the manufacturing complexity and stress concentration increase
Solution Approach 1:
The through-silicon vias are implemented in a segmented manner across multiple bonding interfaces rather than creating single long vias through the entire stack. Each via is formed and filled during the chip fabrication process before stacking, simplifying the manufacturing process while maintaining high-speed vertical interconnection capability.
Solution Approach 2:
The through-silicon vias are formed and prepared in advance during the semiconductor chip manufacturing process, before the stacking and bonding operations. This preliminary action allows the vias to be precisely positioned and filled with conductive material, reducing manufacturing complexity during the final assembly while ensuring high-speed signal transmission paths are ready for operation.
3Productivity
If multiple bonding interfaces are created for stacking, then the integration density is improved, but the stress concentration and bonding defects increase
Solution Approach 1:
The patent introduces a chip bonding insulation layer specifically at the bonding interfaces between stacked chips. This layer is positioned locally at the critical bonding regions to distribute stress and prevent stress concentration that would otherwise occur at the metal bonding pads. The insulation layer maintains electrical connectivity while mechanically cushioning the bonding interface.
Solution Approach 2:
The chip bonding insulation layer acts as an intermediary between the metal bonding pads and the semiconductor substrates at each bonding interface. This intermediate layer mediates the stress distribution, preventing direct stress concentration on the bonding pads while maintaining the electrical connection through the bonding process. The stress reduction member at the inactive surface also serves as a mediator to distribute thermal and mechanical stresses.
Data Source
AI summary
A semiconductor package includes a first semiconductor chip that includes a first semiconductor substrate that includes an active surface and an inactive surface opposite to each other and a plurality of first through silicon vias that penetrate through the first semiconductor substrate, and a plurality of second semiconductor chips that each include a second semiconductor substrate that includes an active surface and an inactive surface opposite to each other and a plurality of second through silicon vias that penetrates through the second semiconductor substrate. Each of the plurality of second semiconductor chips is stacked on the first semiconductor chip, such that the active surface of each second semiconductor substrate faces the inactive surface of the first semiconductor substrate, and the plurality of second semiconductor chips have the same vertical height.