Wafer-Level TSV Encapsulation for Stacked Semiconductor Packages
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Solution Overview
Problem
Existing techniques face challenges in effectively stacking semiconductor packages while controlling the width and height of package-on-package (PoP) structures, which is crucial for reducing size and increasing integration in electronic devices.
Innovation Solution
A method involving the formation of through silicon vias (TSVs) and encapsulants using a wafer level molding process, allowing for the division of semiconductor packages and the stacking of additional packages electrically connected via these vias, thereby controlling the size and electrical connectivity of PoP structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If multiple semiconductor packages are stacked to reduce horizontal mounting surface, then the degree of integration is improved, but the width and height of the PoP structure become difficult to control
Solution Approach 1:
The patent divides the semiconductor package into multiple independent layers (first semiconductor package, second semiconductor package, intermediate substrate) that can be manufactured separately and then stacked. Each layer is processed independently using wafer-level techniques, allowing precise control of individual layer dimensions before assembly, thereby maintaining manufacturing precision while achieving vertical integration.
Solution Approach 2:
The patent transitions from horizontal arrangement of semiconductor packages to vertical stacking configuration. By moving from a two-dimensional layout to a three-dimensional stacked architecture, the solution reduces the horizontal mounting surface area while managing vertical height through controlled layer thicknesses and intermediate substrates.
2Reliability
If through silicon vias are used to connect stacked packages, then electrical connectivity is improved, but the complexity of the manufacturing process increases
Solution Approach 1:
The patent forms through silicon vias and conductive plugs during the wafer-level processing stage, before the packages are separated and stacked. This preliminary formation of interconnection structures eliminates the need for complex post-assembly via drilling and plating operations, reducing manufacturing complexity while ensuring reliable electrical connectivity between stacked packages.
Solution Approach 2:
The patent combines multiple manufacturing operations into a unified wafer-level process. Through vias, conductive plugs, and encapsulation are all formed simultaneously during the wafer processing stage, merging separate complex steps into a single integrated manufacturing flow that reduces overall process complexity.
Data Source
AI summary
Provided is a method of forming a package-on-package. An encapsulation is formed to cover a wafer using a wafer level molding process. The wafer includes a plurality of semiconductor chips and a plurality of through silicon vias (TSVs) passing through the semiconductor chips. The encapsulant may have openings aligned with the TSVs. The encapsulant and the semiconductor chips are divided to form a plurality of semiconductor packages. Another semiconductor package is stacked on one selected from the semiconductor packages. The other semiconductor package is electrically connected to the TSVs.