Through Silicon Via Stacking for High I/O Density
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Solution Overview
Problem
Current integrated circuit packaging systems face challenges in achieving high input/output density, low cost, and improved reliability as they strive to miniaturize and increase functionality, with prior solutions failing to effectively address these needs.
Innovation Solution
The implementation of a packaging system with a bottom integrated circuit featuring bottom through silicon vias and outer interconnects, along with a top integrated circuit having top through silicon vias with a pitch less than the bottom via pitch, allowing for reduced profile and increased patterning flexibility, which enhances signal reliability and enables cost-effective stacking.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If through silicon vias are used to increase input/output density, then electrical interconnection capability is improved, but manufacturing complexity increases
Solution Approach 1:
The patent divides the interconnection system into multiple through silicon via layers, with each layer providing a subset of the total input/output connections. This segmentation allows the complex high-density interconnection task to be broken into manageable manufacturing steps, where each via layer can be processed and tested independently before stacking with other layers.
Solution Approach 2:
The patent transitions from planar interconnection to three-dimensional vertical interconnection by stacking multiple integrated circuit layers with through silicon vias. This dimensional change enables significantly higher input/output density by utilizing the vertical space between stacked dies, effectively adding a third dimension to the interconnection architecture.
2Volume of moving object
If miniaturization is pursued to reduce product size, then device dimensions are reduced, but reliability challenges increase
Solution Approach 1:
The patent embeds multiple integrated circuit dies within a compact stacked configuration, with each die containing complete functional circuits. The through silicon vias are nested within the silicon substrate of each die, creating a dense nested structure that achieves miniaturization while maintaining the functional integrity and reliability of individual circuit components.
Solution Approach 2:
The patent changes the physical parameters of the interconnection system by transitioning from lateral wire routing to vertical through-silicon via routing. This parameter change in the interconnection geometry reduces the planar footprint while the via structure itself provides reliable electrical pathways through the miniaturized stacked architecture, overcoming the reliability challenges of miniaturization.
3Quantity of substance
If via pitch is reduced to increase interconnection density, then electrical connection density is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent performs preliminary alignment and positioning of the through silicon vias during the semiconductor fabrication process, before the stacking and bonding operations. This preliminary action ensures that the vias are precisely positioned with the required pitch and alignment, reducing the precision demands on subsequent assembly steps and enabling higher via density to be achieved.
Data Source
AI summary
A method of manufacture of an integrated circuit packaging system includes: providing a bottom integrated circuit having bottom through silicon vias with a bottom via pitch; mounting outer interconnects over the bottom integrated circuit; and mounting a top integrated circuit between the outer interconnects, the top integrated circuit having top through silicon vias with a top via pitch less than the bottom via pitch.