TSV Stacking Package Structure for Thermal Dissipation
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Solution Overview
Problem
Conventional semiconductor package technologies face challenges in meeting the demands of high-density, small-sized, and high-performance packaging due to inefficiencies in thermal dissipation, electrical signal propagation, and the limitations of traditional lead frame and BGA packages, particularly in handling different die sizes and providing reliable connections without lead-based materials.
Innovation Solution
A semiconductor device package structure featuring a first die with through silicon via (TSV) connections, a build-up layer, and a substrate with conductive through holes, along with a method of forming solder balls and adhesion materials for embedding a second die, allowing for flexible chip stacking and improved thermal and electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If traditional lead frame package or BGA package is used, then the package can provide basic electrical connections, but the thermal dissipation performance is poor and the package size cannot be reduced further
Solution Approach 1:
The patent transitions from planar packaging to three-dimensional stacking architecture, where multiple dies are vertically arranged and connected through through-silicon-vias. This vertical integration enables improved thermal dissipation pathways while reducing the footprint area, directly addressing the contradiction between thermal performance and package size.
Solution Approach 2:
The patent embeds one die inside another die structure, with smaller dies positioned within cavities of larger dies. This nesting approach maximizes space utilization, reduces overall package area, and creates efficient thermal conduction pathways from inner to outer dies, resolving the trade-off between compact size and thermal management.
2Productivity
If conventional package techniques are used, then the manufacturing process is established, but the process is time-consuming and cannot meet high-density requirements
Solution Approach 1:
The patent performs preliminary actions by pre-forming through-silicon-vias and embedding passive components within dies before final assembly. This advance preparation enables faster subsequent assembly steps and allows parallel processing of multiple dies, thereby improving manufacturing efficiency while maintaining high-density precision requirements.
Solution Approach 2:
The patent combines multiple manufacturing operations into integrated processes, such as forming TSVs and embedding components simultaneously during die fabrication. This merging of steps reduces total process time and enables high-density packaging to be achieved without proportionally increasing manufacturing complexity, thus improving productivity.
3Reliability
If solder bumps are used for connections, then electrical connections can be established, but the solder joints exhibit increased electrical resistance and cracks over time due to fatigue
Solution Approach 1:
The patent extracts the problematic solder bump layer from the connection structure and replaces it with direct copper-to-copper bonding through TSVs. This elimination of the solder interface removes the source of fatigue-induced cracks and resistance increase, significantly improving connection reliability while simplifying the overall connection architecture.
Solution Approach 2:
The patent employs composite material structures in the TSV construction, using copper for low-resistance conduction, barrier layers for diffusion prevention, and adhesive layers for mechanical bonding. This multi-material approach creates a reliable, fatigue-resistant connection that outperforms traditional solder joints while maintaining structural integrity.
4Ease of manufacture
If lead-based solder materials are used, then soldering can be performed, but environmental concerns over toxic materials disposal and leaching arise
Solution Approach 1:
The patent removes lead-based solder materials from the connection process entirely, replacing them with lead-free alternatives such as pure copper or copper alloy TSVs. This extraction of toxic materials eliminates environmental hazards associated with lead disposal and leaching, while the ease of manufacture is maintained through optimized copper bonding processes.
Data Source
AI summary
The semiconductor device package structure includes a first die with a through silicon via (TSV) open from back side of the first die to expose bonding pads; a build up layer coupled between the bonding pads to terminal metal pads by the through silicon via (TSV); a substrate with a second die embedded inside and top circuit wiring and bottom circuit wiring on top and bottom side of the substrate respectively; and a conductive through hole structure coupled between the terminal metal pads to the top circuit wiring and the bottom circuit wiring.