TSV Stress Isolation Structure for Current Matching in 3D ICs
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In 3D integrated circuits, through substrate vias (TSV) induce tensile stress, leading to mismatched current conduction between n-type and p-type metal-oxide semiconductors, which conventional keep out zones attempt to mitigate but at the cost of increased circuit area.
Innovation Solution
A semiconductor device with a compound semiconductor structure surrounding the TSVs, introducing a compressive stress that neutralizes the tensile stress from the TSVs, thereby eliminating stress impact on other elements and allowing for reduced keep out zones and smaller circuit area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through substrate vias are used to achieve effective electrical connection in 3D integrated circuits, then electrical connection is improved, but tensile stress from TSVs causes current mismatch between n-type and p-type metal-oxide semiconductors
Solution Approach 1:
A compound semiconductor structure is introduced as an intermediary between the TSVs and the metal-oxide semiconductor devices. This compound semiconductor structure has different stress characteristics than the TSVs, acting as a stress mediator that prevents direct stress transmission to the devices, thereby maintaining electrical connection while reducing current mismatch.
Solution Approach 2:
The patent changes the stress parameter by introducing a compound semiconductor structure with different material properties and stress characteristics. By selecting materials with appropriate lattice constants and mechanical properties, the stress state in the region surrounding the TSVs is modified, reducing the harmful tensile stress effects on the metal-oxide semiconductors.
2Manufacturing precision
If a keep out zone is disposed to isolate TSVs from other semiconductor elements, then current matching is improved, but circuit area increases
Solution Approach 1:
The compound semiconductor structure serves as an intermediary that eliminates the need for a large keep out zone. By placing this structure between the TSVs and other semiconductor elements, stress isolation is achieved with minimal spacing, allowing compact circuit design while maintaining current matching precision.
Solution Approach 2:
Instead of creating a large uniform keep out zone, the patent applies local quality by placing a specifically engineered compound semiconductor structure only in the critical stress region around the TSVs. This localized approach provides stress isolation where needed while minimizing the overall area impact on the circuit design.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The compound semiconductor structure effectively neutralizes the stress from TSVs, improving current matching between n-type and p-type metal-oxide semiconductors without increasing the circuit area, thus enhancing the benefits of 3D integrated circuits.
Implementation Method 1
The compound semiconductor structure has a second stress type different from the first stress type... effectively neutralizes the stress from TSVs, improving current matching between n-type and p-type metal-oxide semiconductors
Data Source
AI summary
A semiconductor device includes: a substrate; a source region and a drain region disposed in the substrate; a shallow trench isolation (STI) region disposed in the substrate and surrounding the source region and the drain region; a plurality of through substrate vias (TSV) through the substrate, wherein the plurality of through substrate vias are adjacent to the shallow trench isolation region; and a compound semiconductor structure isolating the shallow trench isolation region from the plurality of through substrate vias. The plurality of through substrate vias have a first stress type, and the compound semiconductor structure has a second stress type different from the first stress type.