Stress Relief Notch for TSV Insulating Layer
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Solution Overview
Problem
Conductive through silicon vias (TSV) in semiconductor devices experience stress due to mismatches in the coefficient of thermal expansion, leading to cracking and degraded electrical performance.
Innovation Solution
Forming notches around conductive TSV and depositing an insulating layer into these notches to provide stress relief and electrical isolation, reducing the mismatch between the conductive TSV and the semiconductor wafer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conductive TSV is formed through the semiconductor wafer, then electrical connection is achieved, but stress and cracking occur due to CTE mismatch
Solution Approach 1:
The patent divides the continuous conductive TSV structure into segmented sections by introducing insulating material layers at intermediate depths. This segmentation allows different portions of the TSV to have different structural characteristics, with some portions having stress-relief features and others maintaining direct electrical connection, thereby resolving the contradiction between electrical connectivity and stress resistance.
Solution Approach 2:
The patent introduces an insulating material as an intermediary element within the TSV structure. This intermediary material serves dual functions: it provides electrical isolation to prevent unwanted current paths while simultaneously acting as a stress-relief layer that accommodates CTE mismatch between the conductive TSV and the semiconductor wafer, thus protecting against cracking.
2Reliability
If insulating layer is deposited around conductive TSV, then stress relief and electrical isolation are achieved, but device complexity increases
Solution Approach 1:
The patent applies preliminary action by forming the insulating material layer at an intermediate depth within the TSV during the manufacturing process, before final electrical connections are established. This preliminary stress-relief structure is built in advance to prevent cracking from occurring during subsequent processing or operation, thereby managing complexity proactively rather than reactively.
Solution Approach 2:
The patent applies local quality by positioning the insulating material layer at a specific intermediate depth within the TSV structure, rather than uniformly throughout. This localized application of insulating material provides stress relief precisely where the CTE mismatch generates maximum stress, while maintaining direct electrical connection in other regions, thus achieving reliability improvement with minimal added complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The insulating layer effectively reduces stress and prevents cracking, enhancing the reliability and performance of semiconductor devices by improving thermal expansion compatibility and electrical isolation.
Implementation Method 1
The conductive TSV are susceptible to stress due to mismatches in the coefficient of thermal expansion (CTE), particular at the junction between the conductive TSV and base material of the semiconductor wafer.
Implementation Method 2
forming a first insulating layer over a surface of the semiconductor die and adjacent to the conductive via
Implementation Method 3
forming a first insulating layer over a surface of the semiconductor die and adjacent to the conductive via
Data Source
AI summary
A semiconductor device has a plurality of conductive vias formed into a semiconductor wafer. A portion of the semiconductor wafer is removed so the conductive vias extend above a surface of the semiconductor wafer. A notch is formed in the semiconductor wafer around each of the conductive vias. The notch around the conductive vias can be formed by wet etching, dry etching, or LDA. A first insulating layer is formed over a surface of the semiconductor wafer and conductive vias and into the notch to provide stress relief between the conductive vias and semiconductor wafer. A portion of the first insulating layer is removed to expose the conductive vias. A first conductive layer and second insulating layer can be formed around the conductive vias. A second conductive layer can be formed over the conductive vias. The notch can extend into the second insulating layer.