TSV Manufacturing via Substrate Bonding and Oxide Layer Formation
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Solution Overview
Problem
The existing methods for manufacturing semiconductor devices with through silicon via (TSV) structures face challenges in controlling the thickness of layers and forming high-quality insulation layers, especially on the bottom surface, where low-temperature processes are required to avoid affecting semiconductor devices and wiring layers.
Innovation Solution
A method involving the bonding of substrates with preformed oxide layers to create a layered substrate, followed by selective etching and polishing to form TSV islands and electrodes, allowing for accurate insulation and device formation without the need for mask alignment, using techniques like direct bonding and anisotropic etching with TMAH or KOH.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If low-temperature processes are used to form insulation layers on the bottom surface, then the existing semiconductor devices and wiring layers are protected from damage, but the quality and thickness control of the insulation layer deteriorates
Solution Approach 1:
The patent applies preliminary action by forming the first insulation layer on the substrate before forming the semiconductor devices and wiring layers. This allows the insulation layer to be formed under optimal conditions (without temperature constraints) before the temperature-sensitive components are added, thus achieving both high quality insulation layer formation and protection of existing devices.
Solution Approach 2:
The patent inverts the conventional sequence by forming the insulation layer first, then adding the temperature-sensitive semiconductor devices and wiring layers. This reversal allows the insulation layer to be formed without temperature constraints, while subsequent low-temperature processes only affect the already-formed insulation layer, not the temperature-sensitive components.
2Manufacturing precision
If conventional TSV manufacturing processes are used, then through vias can be formed, but the process complexity increases due to multiple steps including mask alignment
Solution Approach 1:
The patent extracts and removes the mask alignment step from the conventional TSV manufacturing process. By using a different approach to define the via regions (through direct patterning or alternative alignment methods), the complex mask alignment procedure is eliminated, reducing overall process complexity while maintaining TSV formation capability.
Solution Approach 2:
The patent applies preliminary action by pre-forming the first insulation layer with defined regions before subsequent processing steps. This preliminary structure provides a foundation that simplifies later via formation steps, eliminating the need for complex mask alignment procedures that would otherwise be required to define via locations.
3Quantity of substance
If layer thickness is reduced to achieve finer structures, then device density increases, but controlling the thickness becomes more difficult
Solution Approach 1:
The patent applies preliminary action by forming the first insulation layer to a specific thickness before adding any temperature-sensitive components. This allows the insulation layer thickness to be precisely controlled under optimal conditions, and this pre-formed layer then serves as a stable foundation for subsequent fine-structure fabrication, enabling both reduced overall thickness and precise control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the efficient manufacturing of high-quality semiconductor devices with improved insulation and reduced processing complexity, allowing for precise control over layer thickness and quality, enhancing device performance and capacity.
Implementation Method 1
the silicon substrate 10 is oxidized to form an oxide film on its surface
Implementation Method 2
low-pressure chemical vapor deposition (CVD) is performed to deposit a polycrystalline silicon film on the oxide film
Implementation Method 3
Phosphosilicate glass (PSG), which is formed through CVD, may be used as the protective layer 15
Implementation Method 4
Chemical-mechanical polishing (CMP) may be performed to grind and polish the silicon substrate 10
Data Source
AI summary
A method for manufacturing a high quality semiconductor device having a through via structure. A substrate is manufactured with an oxide layer including a window region in a region in which a through via is formed. The substrate is bonded with another substrate to form an SOI substrate. The SOI substrate is ground to reduce its thickness. An island region is formed in a region at which a TSV (Through Silicon Via) structure is formed. A device and a TSV are coupled by a wire. The silicon substrate at a bottom side of the SOI substrate is removed to expose the island region from the bottom. A back contact for the TSV is formed in the window region, which is formed in a buried oxide layer.