TSV Template Wafer for 3D Interconnection
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Solution Overview
Problem
Conventional etching and filling processes for Through Silicon Via (TSV) trenches, with increased depth-to-width ratios due to scaling down, face challenges in meeting industrial requirements for semiconductor devices, leading to difficulties in manufacturing efficient 3D interconnection structures.
Innovation Solution
A method involving a TSV template wafer with uniformly distributed TSV holes, filled with conductive material, and a sandwich structure formed by bonding production wafers, where connection parts are created through photolithography and etching to facilitate electrical connections between wafers, using a semiconductor wafer thinned to 2-200 nm and conductive materials like Cu, Al, or TiN.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If TSV trenches are scaled down to reduce feature sizes, then interconnection density is improved, but etching and filling processes become increasingly difficult due to increased depth-to-width ratio
Solution Approach 1:
The patent applies preliminary action by pre-forming TSV holes in a template wafer before bonding to production wafers. This allows the TSV structure to be prepared in advance with optimal dimensions and conductivity, avoiding the difficulty of forming deep narrow trenches after wafer stacking. The template wafer serves as a pre-prepared interconnection framework that simplifies subsequent processing steps.
Solution Approach 2:
The manufacturing process is segmented into separate stages: template wafer preparation with TSV holes, production wafer fabrication, and subsequent bonding. This segmentation allows each component to be optimized independently - the template wafer can be specifically designed for TSV formation while production wafers focus on device fabrication, thereby reducing overall process complexity despite high interconnection density requirements.
2Adaptability or versatility
If conventional etching and filling processes are used for scaled-down TSVs, then existing manufacturing capabilities are maintained, but industrial requirements for 3D interconnection cannot be met
Solution Approach 1:
By pre-forming TSV holes in the template wafer before bonding, the patent achieves reliable 3D interconnection structures without relying on advanced conventional etching and filling processes. The preliminary formation of conductive TSV holes in the template wafer ensures meeting industrial requirements, while the overall approach remains compatible with existing manufacturing capabilities through standard photolithography and etching techniques.
3Reliability
If TSV holes are filled with conductive material and then planarized, then electrical connection is improved, but alignment complexity increases
Solution Approach 1:
The template wafer with pre-formed TSV holes serves as an alignment reference structure. The uniform distribution and predetermined positions of TSV holes provide natural alignment markers that simplify the bonding process. Production wafers can be aligned to the template wafer using these TSV features, reducing alignment complexity while ensuring reliable electrical connections through the conductive material-filled TSV holes.
Solution Approach 2:
The template wafer acts as a master pattern that defines the interconnection geometry. By copying this template structure through bonding with production wafers, the alignment complexity is transferred to the template fabrication stage rather than the assembly stage. The uniform TSV hole pattern in the template serves as a reusable alignment reference for multiple production wafers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method simplifies the etching and filling processes, enhances electrical connection convenience, and improves alignment and design for 3D devices by forming a sandwich structure with uniformly distributed TSVs, reducing the complexity of TSV trench formation and interconnection.
Implementation Method 1
the conductive material is filled in the TSV holes by immersing the TSV template wafer in melted Al and then cooling it down
Implementation Method 2
the conductive material is filled in the TSV holes by immersing the TSV template wafer in melted Al and then cooling it down
Implementation Method 3
The TSV template wafer comprises a semiconductor wafer, which is thinned by 2-200 nm in thickness
Data Source
AI summary
In a method for manufacturing a semiconductor, a Through Silicon Via (TSV) template wafer and production wafers form a sandwich structure, in which the TSV template wafer has TSV structures uniformly distributed therein, for providing electrical connection between the production wafers to form 3D interconnection. The TSV template wafer is obtained by thinning a semiconductor wafer, which facilitates reducing the difficulty in etching and filling. Connection parts are provided on the TSV template wafer, for convenience of interconnection between the overlying and underlying production wafers, which facilitates reducing the difficulty in alignment and improving the convenience of design of electrical connection for 3D devices.