TSV Testing via Serial Parallel Data Routing

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Solution Overview

Problem

The challenge lies in effectively testing whether through-silicon vias (TSVs) in semiconductor systems are properly formed, especially in multi-chip packages, where traditional testing methods are inefficient and may not minimize the circuit area required for testing.

Innovation Solution

A semiconductor system design that includes specific pad configurations and selection units within semiconductor devices, allowing for serial and parallel data input/output operations through through vias, enabling efficient testing of TSV formation by comparing input and output data patterns.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional testing methods are used for through-silicon vias, then testing can be performed, but the circuit area required for testing is not minimized and testing efficiency is reduced

Engineering Contradiction:
ImproveTSV formation testingVSAvoidcircuit area for testing
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies multi-functionality by enabling existing semiconductor device circuits to perform dual purposes: normal operational functions and TSV testing functions. The test input pad and test output pad are integrated into the existing device architecture, allowing the same device to serve both operational and testing roles without requiring separate dedicated testing circuits, thereby minimizing additional circuit area while maintaining reliable TSV formation testing capability

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Measurement precision

If dedicated testing circuits are added for TSV testing, then testing accuracy improves, but the circuit area increases

Engineering Contradiction:
ImproveTSV testing accuracyVSAvoidcircuit area
Core Design Contradiction:
Measurement precisionVSArea of stationary object

Solution Approach 1:

The patent implements self-service by designing a testing mechanism where the semiconductor device itself performs the TSV testing using its own internal circuits and resources. The device uses its existing data storage and transfer capabilities to conduct the testing, eliminating the need for external or dedicated testing equipment that would occupy additional circuit area. This self-testing approach maintains high measurement precision while minimizing the area occupied by testing infrastructure

Inventive Principle:
Principle #25Self-service

3Adaptability or versatility

If multiple pads and selection units are added for testing, then TSV testing capability is enhanced, but the device complexity increases

Engineering Contradiction:
ImproveTSV testing capabilityVSAvoidcircuit structure
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent applies segmentation by dividing the testing function into distinct modular components: a test input pad for data entry, a test output pad for result extraction, and selection units that selectively route data between normal operation and testing modes. This segmented approach allows each component to perform a specific function efficiently, enhancing overall TSV testing capability while keeping the added complexity manageable through clear functional separation and modular design

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS9524952B2Semiconductor system
Publication Date: 2016.12.20 SK HYNIX INC
  • US9524952B2 patent drawing
  • US9524952B2 patent drawing
  • US9524952B2 patent drawing

AI summary

A semiconductor system may include first semiconductor device including a first pad, a second pad and a first test input pad, and suitable for storing data inputted in series through the first test input pad and outputting the stored data in parallel through the first pad and the second pad; a second semiconductor device including a third pad, a fourth pad and a second test output pad, and suitable for storing data inputted in parallel through the third pad and the fourth pad, a first through via connecting the first pad and the third pad so that the stored data outputted in parallel through the first pad is inputted in parallel through the third pad; and a second through via connecting the second pad and the fourth pad so that the stored data outputted in parallel through the second pad is inputted in parallel through the fourth pad.