TSV Testing via eFuse Series Chains in 3D IC Stacks
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Solution Overview
Problem
The challenge in 3D IC manufacturing lies in limited test access and single-ended measurements for through-silicon-vias (TSVs), which hinders effective defect detection and increases yield loss, especially in high-density TSVs and memory-on-logic stacking applications.
Innovation Solution
The method involves using electrical fuse (eFuse) cells to test TSVs before and after bonding in a 3D IC stack, forming eFuse cells between TSVs and connecting them in series with a Flip Flop and delay circuit to apply DC signals and monitor transmission rates, allowing for pre-bond and post-bond testing with high defect sensitivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional TSV test circuits are used for each TSV, then defect detection sensitivity is improved, but device complexity and manufacturing impracticality increase for high-density TSVs
Solution Approach 1:
Multiple TSVs are merged into a single test chain by connecting them in series through the eFuse cell. Instead of having separate test circuits for each TSV, the patent combines multiple TSVs (first TSV, second TSV, third TSV) into one continuous electrical path that shares common test circuitry (Flip Flop, delay circuit), thereby reducing overall device complexity while maintaining defect detection capability across all TSVs
Solution Approach 2:
The eFuse cell serves multiple functions: it acts as a programmable switch to enable/disable specific TSVs in the test chain, provides defect detection capability, and allows for post-bond testing. This multi-functional component replaces what would otherwise require separate dedicated test circuits for each TSV, reducing device complexity while maintaining high defect detection sensitivity
2Ease of operation
If single-ended measurements are used due to limited test access, then test access simplicity is improved, but measurement precision and defect detection capability deteriorate
Solution Approach 1:
The patent transitions from single-ended measurement (one access point) to differential measurement (two access points) by utilizing both the top surface and bottom surface of the wafer for probing TSVs. Test probes access the top surface while reference probes access the bottom surface, creating a differential measurement path that enhances defect detection sensitivity while maintaining operational simplicity
3Reliability
If pre-bond testing is implemented, then yield is improved, but test access complexity increases for multi-tier stacks
Solution Approach 1:
TSVs are tested and verified for defects before the bonding process occurs. The eFuse cells are programmed and TSV functionality is confirmed in the pre-bond state, allowing defective TSVs to be identified and excluded before irreversible bonding takes place. This preliminary testing action improves yield by preventing defective dies from being stacked, while the series chain configuration keeps test access complexity manageable
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables effective detection of defects like breaks and voids in TSVs with high sensitivity, facilitating the testing of high-density TSVs and improving yield by allowing for pre-bond and post-bond testing, thus addressing the limitations of traditional TSV testing methods.
Implementation Method 1
The TSV acts as a load capacitor with respect to a test stimulus
Implementation Method 2
A Flip Flop (FF) 105 is used to store the OutSensing signal at the TSV Test Circuit output compared to the signal from the Delay Circuit 107
Data Source
AI summary
Methods of testing TSVs using eFuse cells prior to and post bonding wafers in a 3D IC stack are provided. Embodiments include providing a wafer of a 3D IC stack, the wafer having thin and thick metal layers; forming first and second TSVs on the wafer, the first and second TSVs laterally separated; forming an eFuse cell between and separated from the first and second TSVs; forming a FF adjacent to the second TSV and on an opposite side of the second TSV from the eFuse cell; connecting the first TSV, the eFuse cell, the second TSV, and the FF in series in an electric circuit; and testing the first and second TSVs prior to bonding the wafer to a subsequent wafer in the 3D IC stack.