TSV Continuity Testing via High Concentration Impurity Regions
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Solution Overview
Problem
In semiconductor devices with via-middle TSVs, it is challenging to detect failures before lamination due to buried TSVs being inaccessible for testing, leading to increased manufacturing costs when a single faulty TSV causes the entire laminated device to be defective.
Innovation Solution
Forming TSVs in a silicon substrate with insulating films covering their interfaces and creating a high concentration impurity region near the bottom surfaces, allowing for pre-lamination testing by connecting a test circuit and inputting a test signal to evaluate TSV continuity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If TSVs are formed as via-middle style with bottom surfaces buried in silicon substrate, then TSV continuity cannot be tested before lamination, but manufacturing cost increases when faulty chips are detected only after lamination
Solution Approach 1:
The patent performs TSV continuity testing before lamination by forming pad electrodes on the bottom surface of the silicon substrate and connecting them to TSV bottom surfaces. This preliminary testing action enables detection of TSV failures prior to the lamination process, allowing defective chips to be identified and removed early, thereby preventing the manufacturing cost increase that would occur if testing were delayed until after lamination.
2Measurement precision
If wafer test pads are used to test transistors, then transistor functionality can be evaluated, but TSV continuity cannot be detected because TSVs are buried and not connected to external circuits
Solution Approach 1:
The patent segments the testing function by creating separate pad electrodes specifically for TSV continuity testing, distinct from the wafer test pads used for transistor functionality evaluation. These dedicated pad electrodes are formed on the bottom surface of the silicon substrate and connected to TSV bottom surfaces, enabling independent TSV continuity measurement without interfering with the existing wafer test pad configuration for transistor testing.
3Ease of operation
If the silicon substrate is thinned and micro bumps are connected to TSV bottom surfaces, then TSVs become accessible for connection, but the pitch between micro bumps is extremely small making wafer testing difficult
Solution Approach 1:
The patent performs the TSV continuity testing action before the substrate thinning and micro bump formation processes. By establishing pad electrodes on the bottom surface of the intact silicon substrate and connecting them to TSV bottom surfaces while the substrate is still at its original thickness, the testing is conducted when alignment is easier and more precise, avoiding the extremely small pitch and thin substrate conditions that would make wafer testing difficult after thinning.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the detection of TSV failures in semiconductor chips before lamination, reducing manufacturing costs by identifying and isolating defective chips early in the process.
Implementation Method 1
providing a high concentration impurity region in a peripheral region of the bottom surface sides of the TSVs in the silicon substrate; inputting a test signal from one of the TSVs and detecting the test signal output via the high concentration impurity region and the other TSV
Data Source
AI summary
A method of manufacturing a semiconductor device according to the present invention includes, in a silicon substrate of the semiconductor chip, providing two TSVs (Through-Silicon-Vias) that are formed such that interfaces with the silicon substrate are covered with insulating films and bottom surface sides thereof do not penetrate through the silicon substrate, providing a high concentration impurity region in a peripheral region of the bottom surface sides of the TSVs in the silicon substrate, connecting a test circuit to the TSVs, inputting a test signal from one of the TSVs and detecting the test signal output via the high concentration impurity region and the other TSV, thereby evaluating a failure of the semiconductor chip, thinning a bottom surface of the semiconductor chip and removing the high concentration impurity region.