Through Substrate Via Testing for Vertical IC Stacks
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor devices shrink, stacking memory chips vertically to reduce size and increase memory in limited space becomes challenging due to manufacturing defects in through-silicon vias (TSVs) that can lead to high resistance and signal delays, affecting power consumption and access time.
Innovation Solution
Implementing a method to test and select high-quality TSVs by measuring resistance and RC delay using sense amps and redundant TSV stacks, allowing for replacement of defective TSVs with better ones to maintain low resistance and short signal paths, thereby improving the reliability of vertical chip stacks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory chips are stacked vertically to reduce device size, then memory capacity in limited space is increased, but manufacturing defects in through-silicon vias cause high resistance and signal delays
Solution Approach 1:
The patent applies preliminary action by implementing resistance and RC delay measurements on TSVs during the manufacturing process, before the chips are stacked. This allows defective TSVs to be identified and replaced with redundant ones while the chips are still on the wafer, preventing reliability issues from propagating into the final stacked device. The early detection and replacement mechanism ensures that only high-quality TSV connections are used in the vertical stack.
2Ease of operation
If through-silicon vias are used to provide electrical connections through substrate, then direct connections between stacked memory chips are achieved, but manufacturing defects lead to high resistance affecting power consumption
Solution Approach 1:
The patent implements preliminary resistance measurements on TSVs during manufacturing, allowing defective high-resistance vias to be identified and replaced with redundant low-resistance ones before stacking. This preliminary screening ensures that the direct electrical connections in the final stacked device have low resistance, thereby minimizing power consumption while maintaining the ease of direct connection advantage.
3Speed
If through-silicon vias are used for vertical chip connections, then signal paths are shortened, but manufacturing defects cause signal delays
Solution Approach 1:
The patent applies preliminary action by performing RC delay measurements on TSVs during the manufacturing process, before chips are stacked. This early detection allows defective TSVs with excessive RC delay to be identified and replaced with redundant ones that meet performance specifications. By screening TSVs before stacking, the patent ensures that the shortened signal paths in the final device maintain both high speed and signal integrity, free from manufacturing defects.
4Reliability
If redundant TSV stacks are implemented for replacement, then defective TSVs can be replaced with better ones, but device complexity increases
Solution Approach 1:
The patent implements preliminary action by performing resistance and RC delay measurements on TSVs during manufacturing, before chips are stacked. This early screening allows defective TSVs to be identified and replaced with redundant ones while the chips are still on the wafer, using simple electrical measurement techniques. By conducting the screening and replacement process during manufacturing rather than in the field, the patent minimizes the added complexity while maximizing reliability improvement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures efficient power management and reduced access time by identifying and replacing defective TSVs, ensuring low resistance and short signal paths, thus enhancing the performance and reliability of vertically stacked semiconductor devices.
Implementation Method 1
measuring resistance and RC delay using sense amps
Implementation Method 2
measuring resistance and RC delay using sense amps
Data Source
AI summary
A stack of vertically-connected, horizontally-oriented integrated circuits (ICs) may have electrical connections from the front side of one IC to the back side of another IC. Electrical signals may be transferred from the back side of one IC to the front side of the same IC by means of through substrate vias (TSVs), which may include through silicon vias. Electronic apparatus, systems, and methods may operate to test and/or replace defective TSVs. Additional apparatus, systems and methods are disclosed.