Memory Macro TSV Structure for Lower-Loss 3D Power Distribution
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing IC packages face challenges in efficient power distribution due to limited TSV density, leading to increased resistance and power losses, especially in 3D stacked configurations.
Innovation Solution
Incorporating TSVs that extend through memory macros, increasing TSV density, and optimizing their placement to reduce resistance and power losses in the power distribution structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If TSV density is increased by extending TSVs through memory macros, then power distribution efficiency is improved, but manufacturing complexity increases
Solution Approach 1:
The patent segments the TSV structure into multiple levels: TSVs extending through memory macros, TSVs between memory macros, and TSVs in interposer layers. This segmentation allows each TSV group to be optimized independently for power distribution while managing manufacturing complexity through modular construction approaches.
Solution Approach 2:
The patent transitions from traditional 2D power distribution to 3D power distribution by extending TSVs through the vertical dimension, including through memory macros and across multiple stacked dies. This dimensional change increases TSV density and creates multiple power distribution pathways, reducing power losses while distributing the manufacturing complexity across different vertical layers.
2Loss of energy
If TSVs are extended through memory macros to increase density, then resistance is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies different TSV configurations to different local regions: TSVs extending through memory macros in regions requiring low resistance, TSVs positioned between memory macros in regions requiring electrical isolation, and TSVs with varying diameters and depths optimized for local power distribution needs. This local quality approach reduces overall resistance while managing precision requirements through region-specific optimization.
Solution Approach 2:
The patent varies TSV parameters including diameter, depth, and material composition across different locations and layers. TSVs extending through memory macros may have different dimensions than TSVs in interposer layers, allowing optimization of resistance characteristics while adapting to local manufacturing precision capabilities through parameter adjustment rather than uniform high-precision requirements.
3Power
If 3D stacked configurations are implemented, then power distribution capability is improved, but device complexity increases
Solution Approach 1:
The patent designs TSVs to serve multiple functions: power distribution, signal transmission, and thermal management. The same TSV infrastructure supports multiple stacked dies with different functionalities (memory macros, logic circuits, I/O interfaces), reducing the need for separate specialized structures and managing complexity through multi-functional integration.
Solution Approach 2:
The patent implements a nested structure where TSVs in interposer layers are positioned to align with and extend into TSVs in substrate layers, creating a hierarchical nested arrangement. This nesting allows power distribution to be organized in concentric layers, improving power delivery capability while managing complexity through systematic alignment and integration of nested structures.
Data Source
AI summary
An integrated circuit (IC) die includes first through third adjacent rows of through-silicon vias (TSVs), and first and second adjacent rows of memory macros. TSVs of the first row of TSVs extend through and are electrically isolated from memory macros of the first row of memory macros. TSVs of the third row of TSVs extend through and are electrically isolated from memory macros of the second row of memory macros.