TSV Structure Using a Top Barrier Layer for Reliable Rear Contact
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Solution Overview
Problem
Current TSV technology is limited by the requirement for significant thickness of the bottom barrier layer and metal layer, making it unsuitable for smaller CMOS nodes and incompatible with different CMOS technologies, as it relies on landing on these layers which can be damaged during etching, leading to unreliable electrical contacts.
Innovation Solution
The implementation of a through-substrate-via (TSV) that penetrates the substrate and metal layer up to a top barrier layer, eliminating the need for a bottom barrier layer and allowing for reliable electrical contact independent of metal layer thickness, using a top barrier layer as an etch stop and to prevent diffusion processes like electromigration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the TSV lands on the bottom barrier layer or metal layer, then electrical contact is established, but the barrier layer or metal layer is damaged due to etching process
Solution Approach 1:
The patent introduces a dedicated etch stop layer positioned between the metal layer and the bottom barrier layer. This intermediary layer serves as a sacrificial element that stops the etching process before it reaches the critical bottom barrier layer and metal layer, thereby preventing etching damage while still enabling electrical contact through the TSV structure.
Solution Approach 2:
The etch stop layer is formed in advance during the metal layer fabrication process, before the TSV etching is performed. This preliminary action ensures that the protective layer is already in place to prevent damage during subsequent etching operations, allowing the TSV to be formed without compromising the integrity of the bottom barrier layer and metal layer.
2Object-affected harmful factors
If the bottom barrier layer thickness is increased to prevent damage, then barrier functionality is maintained, but the process becomes incompatible with smaller CMOS nodes and different foundries
Solution Approach 1:
The protective function is segmented into two distinct components: the original bottom barrier layer (which maintains its standard thickness for compatibility) and a separate etch stop layer (which provides the additional protection). This segmentation allows each layer to fulfill its specific function independently, preserving compatibility with existing CMOS processes while adding the necessary protection.
Solution Approach 2:
The etch stop layer acts as a mediator between the etching process and the bottom barrier layer. It absorbs the harmful etching effects that would otherwise require increasing the bottom barrier layer thickness, thereby maintaining compatibility with various CMOS technologies and foundry processes while still providing adequate protection.
3Length of moving object
If the metal layer thickness is reduced for smaller nodes, then device scaling is achieved, but the TSV cannot reliably contact the metal layer
Solution Approach 1:
The etch stop layer serves as a mediator that decouples the TSV etching process from the metal layer thickness. By providing a dedicated stopping point for the etch, it ensures reliable TSV formation and electrical contact regardless of the metal layer thickness, enabling safe reduction of metal layer thickness for smaller CMOS nodes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability of TSVs by ensuring consistent and reliable electrical contact without dependence on metal or bottom barrier layer thickness, enabling compatibility with various CMOS technologies and extending usability to smaller nodes.
Implementation Method 1
A TSV is an electric interconnection through a semiconductor substrate. It comprises a via hole penetrating the substrate and a metallization arranged in the via hole. Barrier layers of a different metallic material covering the metal layer improve the adhesion of the intermetal dielectric and prevent diffusion processes like electromigration.
Implementation Method 2
The insulating layer and the intermetal dielectric are removed from the bottom of the via hole by an anisotropic etching step, such that the insulating layer remains on the sidewall to cover the semiconductor material.
Data Source
AI summary
A semiconductor device includes a substrate—with a rear surface and a main surface, an intermetal dielectric on the main surface of substrate, a metal layer embedded in the intermetal dielectric. The metal layer includes a top barrier layer. The top barrier layer is at a side of the metal layer facing away from the substrate. The semiconductor device also includes a through-substrate-via (TSV) reaching from the rear surface of the substrate to the top barrier layer of the metal layer. The TSV includes a metallization configured to electrically contact the metal layer from the rear surface of the substrate. The TSV includes a via hole. The via hole penetrates the substrate and the intermetal dielectric between the substrate and the metal layer. The via hole further penetrates the metal layer up to the top barrier layer.