Topside Power Delivery Pathways for Flexible Multi-Die IC Packaging
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Communicating large numbers of signals in a multi-die IC package is challenging due to design complexities and constraints associated with power delivery, signal interconnects, and space competition on the IC package.
Innovation Solution
The implementation of a microelectronic assembly with a topside power delivery pathway, utilizing through-substrate vias (TSVs) and redistribution layers (RDLs) to efficiently deliver power to microelectronic components, reducing the need for a large number of power interconnects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If traditional power delivery methods are used in multi-die IC packages, then power can be delivered to components, but the number of power interconnects increases significantly, increasing device complexity and reducing design flexibility
Solution Approach 1:
The patent introduces through-substrate vias (TSVs) that extend vertically through the substrate, transitioning power delivery from a planar two-dimensional layout to a three-dimensional structure. This vertical dimension allows power to be delivered directly to the backside of dies, reducing the need for extensive lateral interconnect routing and thereby reducing overall device complexity while maintaining design flexibility.
Solution Approach 2:
The patent employs a substrate with integrated TSVs and redistribution layers (RDLs) as an intermediary structure between the power source and the microelectronic components. This intermediary substrate acts as a power distribution network that consolidates and routes power efficiently, reducing the number of direct power interconnects needed between individual components and the power source.
2Area of stationary object
If traditional power delivery methods are used in multi-die IC packages, then power can be delivered to components, but the IC package size increases due to space requirements for numerous power interconnects
Solution Approach 1:
By utilizing the vertical dimension through TSVs, the patent enables power delivery without requiring additional lateral space for extensive interconnect routing. The power distribution network is folded into the vertical dimension, allowing the IC package to maintain a compact footprint while ensuring reliable power delivery to all components.
Solution Approach 2:
The patent embeds multiple functional layers within the substrate structure, including TSVs, RDLs, and microelectronic components, in a nested configuration. The TSVs are embedded within the substrate, RDLs are formed on substrate surfaces, and components are mounted on these layers, creating a compact nested structure that maximizes space utilization and ensures reliable power delivery.
3Ease of manufacture
If traditional power delivery methods are used in multi-die IC packages, then power can be delivered to components, but manufacturing complexity and costs increase
Solution Approach 1:
The patent forms TSVs and RDLs on the substrate before mounting the microelectronic components. This preliminary preparation of the power distribution network simplifies the overall manufacturing process, as the substrate serves as a pre-configured power delivery platform that requires minimal additional processing after component attachment, thereby reducing manufacturing complexity while ensuring reliable power delivery.
Solution Approach 2:
The patent divides the power distribution function into separate modular components: TSVs for vertical power transport, RDLs for lateral power routing, and component mounting areas. This segmentation allows each element to be optimized and manufactured independently using standard semiconductor fabrication processes, reducing overall manufacturing complexity while maintaining reliable power delivery performance.
Data Source
AI summary
Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate including a first conductive pathway electrically coupled to a power source; a first microelectronic component, embedded in an insulating material on the surface of the package substrate, including a through-substrate via (TSV) electrically coupled to the first conductive pathway; a second microelectronic component embedded in the insulating material; and a redistribution layer on the insulating material including a second conductive pathway electrically coupling the TSV, the second microelectronic component, and the first microelectronic component.