TSV Metallization via Tungsten Barrier CVD
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Solution Overview
Problem
Current methods for through silicon via (TSV) metallization in semiconductor devices face challenges in efficiently filling high aspect ratio vias with conductive materials while managing thermal stress and maintaining cost-effectiveness, especially for 3D integrated circuits where vias have high aspect ratios and small diameters.
Innovation Solution
A method involving the deposition of a dielectric layer over through silicon vias, followed by a tungsten barrier layer using CVD or ALD, and an intermediate adhesion transition layer, allowing for conductive filling through electroless or electroplating processes, which reduces thermal stress and costs by using conformal deposition techniques like CVD and ELD.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional TSV metallization methods are used, then via filling can be achieved, but thermal stress increases and manufacturing cost increases
Solution Approach 1:
The patent changes the deposition parameters by using CVD or ALD processes to form a tungsten barrier layer with specific properties that reduce thermal stress. The barrier layer is formed with controlled thickness and composition parameters to minimize thermal mismatch between the via fill material and surrounding structures, thereby reducing thermal stress while maintaining reliable via filling.
Solution Approach 2:
The patent employs a composite structure consisting of a tungsten barrier layer combined with a dielectric layer and conductive fill material. This composite material approach allows optimization of each layer's properties to collectively reduce thermal stress - the tungsten barrier provides mechanical strength and stress management, while the dielectric layer provides insulation and stress distribution, achieving reliable via filling with reduced thermal stress.
2Reliability
If conventional TSV metallization methods are used, then via filling can be achieved, but manufacturing cost increases
Solution Approach 1:
The patent performs preliminary action by forming the tungsten barrier layer and dielectric layer structure before via filling. This preliminary preparation optimizes the via structure in advance, ensuring that subsequent filling operations proceed efficiently with reduced material waste and fewer rework steps, thereby maintaining high via filling quality while reducing overall manufacturing cost.
Solution Approach 2:
The patent implements self-service through the conformal deposition process where the CVD or ALD methods automatically form uniform barrier layers that conform to the via geometry. This self-adjusting deposition process eliminates the need for complex manual intervention or additional planarization steps, reducing manufacturing complexity and cost while ensuring consistent via filling quality.
3Productivity
If high aspect ratio vias are filled, then 3D IC interconnection is achieved, but uniform barrier layer formation becomes difficult
Solution Approach 1:
The patent replaces mechanical deposition methods with CVD or ALD processes that use chemical vapor deposition mechanisms. These processes allow precursor gases to diffuse and react conformally on the via walls, achieving uniform barrier layer formation even in high aspect ratio vias where mechanical methods would fail to provide consistent coating thickness.
Solution Approach 2:
The patent changes the deposition parameters by using controlled temperature, pressure, and gas flow conditions in CVD or ALD processes. These parameter optimizations ensure that the barrier layer forms uniformly throughout high aspect ratio vias, with consistent thickness and composition, enabling reliable 3D IC interconnection while maintaining manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient filling of through silicon vias with reduced thermal stress and lower costs, achieving uniform barrier layers even at high aspect ratios, and potentially reducing planarization needs, thereby enhancing the metallization process for 3D ICs.
Implementation Method 1
A barrier layer, comprising tungsten, is deposited by CVD or ALD over the dielectric layer
Implementation Method 2
A barrier layer, comprising tungsten, is deposited by CVD or ALD over the dielectric layer
Data Source
AI summary
To achieve the foregoing and in accordance with the purpose of the present invention, a method for filling through silicon vias is provided. A dielectric layer is formed over the through silicon vias. A barrier layer, comprising tungsten, is deposited by CVD or ALD over the dielectric layer. The through silicon vias are filled with a conductive material.