TSV U-FET for Dielectric Liner Integrity Characterization
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Solution Overview
Problem
Conventional Through-Silicon-Vias (TSVs) are unable to effectively characterize the integrity of the dielectric liner, particularly when it is cracked or experiences copper diffusion, leading to electrical current leakage and degradation of semiconducting properties, limiting the accuracy of electrical measurements and device performance.
Innovation Solution
A U-shaped FET structure with a through-substrate via (TSV U-FET) is created, utilizing an epitaxial layer and annular TSV, with three terminals, including a metal stack that contacts the n++ epitaxial layer without direct connection to the TSV, allowing for characterization of the TSV dielectric liner integrity through advanced imaging and electrical measurements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional TSV with metal pad contact is used, then electrical connections can be made through substrate, but measurement accuracy deteriorates due to leakage and oxide variation in large area
Solution Approach 1:
The patent segments the measurement area by using an annular TSV structure with inner and outer regions separated by the TSV annulus. This segmentation isolates the measurement to a specific channel region, reducing the impact of leakage and oxide variation across large areas, thereby improving measurement precision while maintaining reliable electrical connections through the segmented path.
Solution Approach 2:
The patent applies local quality by creating a specific channel structure where the semiconducting material forms a defined path between inner and outer regions. This localized channel structure ensures that measurements are taken in a controlled region with specific electrical properties, improving measurement accuracy while maintaining overall connection reliability through the localized measurement path.
2Reliability
If TSV dielectric liner is physically cracked, then electrical current flow increases between TSV metal and substrate, but detection capability deteriorates
Solution Approach 1:
The patent implements feedback by using the U-shaped FET structure to continuously monitor the electrical properties of the TSV dielectric liner. The FET's channel current provides real-time feedback on the liner's integrity, allowing detection of cracks through changes in electrical characteristics. This feedback mechanism enables both maintenance of electrical isolation and simultaneous detection of liner degradation.
Solution Approach 2:
The patent introduces the U-shaped FET channel as an intermediary structure between the TSV metal and substrate. This intermediary channel allows indirect detection of dielectric liner integrity through electrical measurements, enabling crack detection while maintaining the primary function of electrical isolation. The FET acts as a mediator that translates physical liner conditions into measurable electrical signals.
3Speed
If copper via structure is used, then high speed signal transmission is achieved, but copper diffusion degrades semiconducting properties
Solution Approach 1:
The patent uses the U-shaped FET channel and dielectric liner as intermediary structures between the copper TSV and the semiconducting material. These intermediaries prevent direct contact between copper and semiconductor, blocking copper diffusion while maintaining high-speed signal transmission through the TSV. The intermediary structures act as protective barriers that preserve signal speed without allowing copper contamination.
Solution Approach 2:
The patent converts the potential harm of copper diffusion into a benefit by using the U-shaped FET structure to detect and monitor copper contamination. The FET's sensitivity to electrical property changes allows it to serve as an early warning system for copper diffusion, enabling preventive measures while maintaining the high-speed transmission benefits of copper TSVs.
4Reliability
If deeper TSV is used, then electrical connections through substrate are improved, but current flow between inner and outer regions decreases
Solution Approach 1:
The patent applies local quality by concentrating the current flow path in a specifically designed U-shaped channel structure. This localized channel provides a controlled path for current between inner and outer regions, ensuring sufficient current flow even in deeper TSV structures. The local quality of the channel structure maintains current flow while the overall deeper TSV structure improves through-substrate connection reliability.
Data Source
AI summary
A through-the silicon via (TSV) structure providing a built-in TSV U-shaped FET that includes an annular gate shaped as a TSV partially embedded in a substrate, the annular gate having an inner and an outer surface bound by an oxide layer; a drain formed on an isolated epitaxial layer on top of the substrate conformally connecting the gate oxide layer surrounding the inner annular surface of the TSV; a source partially contacting said gate oxide layer conformally contacting gate oxide layer surrounding the outer surface of the TSV.