Through Silicon Vias Microloading Reduction via Unified Etching
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Solution Overview
Problem
The manufacturing process of through silicon vias (TSVs) is cumbersome due to the need for separate photoresist patterning and etching processes for thermal and electrical vias, leading to microloading effects that reduce etch rates and heat dissipation efficiency, as thermal conductivity of silicon is lower than metal-filled trenches.
Innovation Solution
Designing thermal and electrical TSVs with the same depth and aspect ratios, using a single photoresist patterning and etching process, and optimizing TSV sizes and densities to minimize microloading effects, allowing thermal TSVs to function as both electrical and thermal connections, thereby simplifying the manufacturing process and enhancing heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If separate photoresist patterning and etching processes are used for thermal and electrical vias, then manufacturing precision can be maintained, but device complexity and manufacturing time increase
Solution Approach 1:
The patent combines the patterning and etching of thermal vias and electrical TSVs into a single integrated process. By designing thermal vias with the same depth and aspect ratio as electrical TSVs, both via types can be etched simultaneously through one photoresist patterning and one etching process, eliminating the need for separate processing steps while maintaining manufacturing precision
Solution Approach 2:
The patent creates a universal via structure where thermal vias and electrical TSVs share the same geometric parameters (depth, aspect ratio). This universality allows a single etching process to serve dual purposes: creating both thermal conduction paths and electrical connections, thereby reducing process complexity while maintaining the specialized functions of each via type
2Manufacturing precision
If separate etching processes are used for thermal and electrical vias, then via quality can be maintained, but productivity decreases
Solution Approach 1:
The patent merges the etching of thermal vias and electrical TSVs into a single etching step. By ensuring both via types have identical depth requirements and aspect ratios, the process achieves uniform etch rates across all vias in one batch, maintaining quality while doubling productivity compared to sequential processing
3Adaptability or versatility
If different via depths are used for thermal and electrical connections, then functional requirements are met, but microloading effects increase
Solution Approach 1:
The patent changes the geometric parameters of thermal vias to match those of electrical TSVs, specifically setting thermal via depth equal to TSV depth and ensuring aspect ratios are identical. This parameter alignment eliminates microloading effects during etching, as the etch rate becomes uniform across all vias regardless of their functional purpose, while still meeting both thermal conduction and electrical connection requirements
Data Source
AI summary
A method of making a support structure is provided. The method includes depositing a photoresist layer on a substrate of the support structure and patterning the photoresist layer. The method further includes etching the patterned photoresist layer. Etching the patterned photoresist includes forming a first group of through silicon vias (TSVs) configured to electrically connect a first surface of the substrate to a first electrical interface adjacent an opposite second surface of the substrate. Etching the patterned photoresist further includes forming a second group of TSVs configured to conduct thermal energy from the first surface of the substrate to a thermal interface adjacent the second surface of the substrate. A difference in cross-sectional area between TSVs in the first group of TSVs and TSVs in the second group of TSVs is less than 10%, and the first electrical interface is separated from the thermal interface.