TSV Validation Structure for Silicon Carbide Etch Connectivity
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Solution Overview
Problem
The etching process for forming through substrate vias (TSVs) in silicon carbide substrates is challenging due to varying thickness and contamination, leading to incomplete formation and difficulty in validating the electrical connectivity of TSVs, which can result in failed RF amplifiers when integrated circuits are tested at high frequencies.
Innovation Solution
A method is introduced to validate the formation of standard TSVs by testing non-standard TSVs, where the size of openings in the lithographic mask is chosen based on empirical testing to ensure proper etching, and conductivity or resistance measurements are used to confirm the formation of both types of TSVs, providing confidence in the electrical connection from the first to the second surface of the substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If etching is performed for a fixed time to form TSVs, then productivity is improved, but manufacturing precision deteriorates due to over-etching or under-etching
Solution Approach 1:
The patent introduces a test structure with a non-standard TSV before production to pre-determine the optimal etching time. This preliminary action allows the etching parameters to be calibrated in advance, ensuring that the subsequent production etching achieves precise TSV formation without over-etching or under-etching, thus resolving the contradiction between productivity and manufacturing precision.
2Measurement precision
If standard TSV formation is validated directly, then measurement precision is improved, but device complexity increases due to difficulty in testing
Solution Approach 1:
The patent introduces a non-standard TSV as an intermediary test object. This non-standard TSV serves as a mediator that is easier to test and validate than standard TSVs. By validating the non-standard TSV, the patent indirectly validates the standard TSV formation process, thus achieving measurement precision while reducing device complexity.
Solution Approach 2:
The patent creates a copy of the TSV structure in the form of a non-standard TSV within the test structure. This copy replicates the essential formation characteristics of standard TSVs but with modified dimensions that make testing easier. Validating the copy (non-standard TSV) provides confidence in the original (standard TSV) formation, simplifying the validation process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures reliable formation and validation of standard TSVs, reducing the risk of incomplete connections and improving the performance of integrated circuits by detecting potential issues before packaging, thereby enhancing the reliability of RF amplifiers.
Implementation Method 1
a mask is applied to a first surface of a substrate that includes a second surface, and the mask is patterned to have a first opening and a second opening; the substrate is etched through the first opening and the second opening for a same etching time to form a first via and a second via
Implementation Method 2
a first conductive material is formed on an interior of the etched substrate within the first via to form a conductive path between the first surface and the second surface; and a second conductive material is formed on an interior of the etched substrate within the second via to form a conductive path from the first surface to the second surface
Data Source
AI summary
An integrated circuit comprises a substrate that includes a first surface and a second surface. A first through substrate via (TSV) is formed between the first surface and the second surface and a first conductive material is arranged within the first TSV to form a conductive path between the first surface and the second surface through the substrate. A second TSV is formed between the first surface and the second surface and a second conductive material arranged within the second TSV to form a conductive path between the first surface and the second surface through the substrate. In examples the first TSV has a larger cross-sectional area than the second TSV, the cross-section of the first TSV and second TSV being in a plane parallel to the first surface or the second surface.